^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_HASH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_HASH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * The later H8SX models have a 32x32-bit multiply, but the H8/300H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * and H8S have only 16x16->32. Since it's tolerably compact, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * basically an inlined version of the __mulsi3 code. Since the inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * are not expected to be small, it's also simplfied by skipping the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * early-out checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (Since neither CPU has any multi-bit shift instructions, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * shift-and-add version is a non-starter.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * TODO: come up with an arch-specific version of the hashing in fs/namei.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * since that is heavily dependent on rotates. Which, as mentioned, suck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * horribly on H8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #if defined(CONFIG_CPU_H300H) || defined(CONFIG_CPU_H8S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HAVE_ARCH__HASH_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Multiply by k = 0x61C88647. Fitting this into three registers requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * one extra instruction, but reducing register pressure will probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * make that back and then some.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * GCC asm note: %e1 is the high half of operand %1, while %f1 is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * low half. So if %1 is er4, then %e1 is e4 and %f1 is r4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This has been designed to modify x in place, since that's the most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * common usage, but preserve k, since hash_64() makes two calls in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * quick succession.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline u32 __attribute_const__ __hash_32(u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) asm( "mov.w %e1,%f0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "\n mulxu.w %f2,%0" /* klow * xhigh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "\n mov.w %f0,%e1" /* The extra instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "\n mov.w %f1,%f0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "\n mulxu.w %e2,%0" /* khigh * xlow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "\n add.w %e1,%f0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "\n mulxu.w %f2,%1" /* klow * xlow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "\n add.w %f0,%e1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) : "=&r" (temp), "=r" (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) : "%r" (GOLDEN_RATIO_32), "1" (x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif /* _ASM_HASH_H */