Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 	compatible = "renesas,edosk2674";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	interrupt-parent = <&h8intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	chosen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 		bootargs = "console=ttySC2,38400";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 		stdout-path = &sci2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	aliases {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 		serial0 = &sci0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 		serial1 = &sci1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		serial2 = &sci2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	xclk: oscillator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		clock-frequency = <33333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		clock-output-names = "xtal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	pllclk: pllclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		compatible = "renesas,h8s2678-pll-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		clocks = <&xclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		reg = <0xffff3b 1>, <0xffff45 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	core_clk: core_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		compatible = "renesas,h8300-div-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		clocks = <&pllclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		reg = <0xffff3b 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		renesas,width = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	fclk: fclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		compatible = "fixed-factor-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		clocks = <&core_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		clock-div = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		clock-mult = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	memory@400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		reg = <0x400000 0x800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			compatible = "renesas,h8300";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			clock-frequency = <33333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	h8intc: interrupt-controller@fffe00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		compatible = "renesas,h8s-intc", "renesas,h8300-intc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		reg = <0xfffe00 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	bsc: memory-controller@fffec0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		reg = <0xfffec0 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	tpu: timer@ffffe0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		compatible = "renesas,tpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		reg = <0xffffe0 16>, <0xfffff0 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		clocks = <&fclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		clock-names = "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	timer8: timer@ffffb0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		compatible = "renesas,8bit-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		reg = <0xffffb0 10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		interrupts = <72 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		clocks = <&fclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		clock-names = "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	sci0: serial@ffff78 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		compatible = "renesas,sci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		reg = <0xffff78 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		interrupts = <88 0>, <89 0>, <90 0>, <91 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		clocks = <&fclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		clock-names = "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	sci1: serial@ffff80 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		compatible = "renesas,sci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		reg = <0xffff80 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		interrupts = <92 0>, <93 0>, <94 0>, <95 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		clocks = <&fclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		clock-names = "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	sci2: serial@ffff88 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		compatible = "renesas,sci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		reg = <0xffff88 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		interrupts = <96 0>, <97 0>, <98 0>, <99 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		clocks = <&fclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		clock-names = "fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };