^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/genalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #if (CONFIG_ITCM_RAM_BASE == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #error "You should define ITCM_RAM_BASE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #if (CONFIG_DTCM_RAM_BASE == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #error "You should define DTCM_RAM_BASE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #if (CONFIG_DTCM_RAM_BASE == CONFIG_ITCM_RAM_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #error "You should define correct DTCM_RAM_BASE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern char __tcm_start, __tcm_end, __dtcm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct gen_pool *tcm_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void __init tcm_mapping_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pte_t *tcm_pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long vaddr, paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) paddr = CONFIG_ITCM_RAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (pfn_valid(PFN_DOWN(CONFIG_ITCM_RAM_BASE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) goto panic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) for (i = 0; i < TCM_NR_PAGES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) for (i = 0; i < CONFIG_ITCM_NR_PAGES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) vaddr = __fix_to_virt(FIX_TCM - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) tcm_pte =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pte_offset_kernel((pmd_t *)pgd_offset_k(vaddr), vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) set_pte(tcm_pte, pfn_pte(__phys_to_pfn(paddr), PAGE_KERNEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) flush_tlb_one(vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) paddr = paddr + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (pfn_valid(PFN_DOWN(CONFIG_DTCM_RAM_BASE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) goto panic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) paddr = CONFIG_DTCM_RAM_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (i = 0; i < CONFIG_DTCM_NR_PAGES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) vaddr = __fix_to_virt(FIX_TCM - CONFIG_ITCM_NR_PAGES - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) tcm_pte =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pte_offset_kernel((pmd_t *) pgd_offset_k(vaddr), vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) set_pte(tcm_pte, pfn_pte(__phys_to_pfn(paddr), PAGE_KERNEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) flush_tlb_one(vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) paddr = paddr + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifndef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) memcpy((void *)__fix_to_virt(FIX_TCM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &__tcm_start, &__tcm_end - &__tcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pr_info("%s: mapping tcm va:0x%08lx to pa:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __func__, __fix_to_virt(FIX_TCM), CONFIG_ITCM_RAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pr_info("%s: __tcm_start va:0x%08lx size:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __func__, (unsigned long)&__tcm_start, &__tcm_end - &__tcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) memcpy((void *)__fix_to_virt(FIX_TCM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) &__tcm_start, &__dtcm_start - &__tcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pr_info("%s: mapping itcm va:0x%08lx to pa:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __func__, __fix_to_virt(FIX_TCM), CONFIG_ITCM_RAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_info("%s: __itcm_start va:0x%08lx size:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __func__, (unsigned long)&__tcm_start, &__dtcm_start - &__tcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) memcpy((void *)__fix_to_virt(FIX_TCM - CONFIG_ITCM_NR_PAGES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &__dtcm_start, &__tcm_end - &__dtcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr_info("%s: mapping dtcm va:0x%08lx to pa:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __func__, __fix_to_virt(FIX_TCM - CONFIG_ITCM_NR_PAGES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CONFIG_DTCM_RAM_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pr_info("%s: __dtcm_start va:0x%08lx size:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __func__, (unsigned long)&__dtcm_start, &__tcm_end - &__dtcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) panic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) panic("TCM init error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void *tcm_alloc(size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!tcm_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) vaddr = gen_pool_alloc(tcm_pool, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return (void *) vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EXPORT_SYMBOL(tcm_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void tcm_free(void *addr, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) gen_pool_free(tcm_pool, (unsigned long) addr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EXPORT_SYMBOL(tcm_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int __init tcm_setup_pool(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifndef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 pool_size = (u32) (TCM_NR_PAGES * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - (u32) (&__tcm_end - &__tcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 tcm_pool_start = __fix_to_virt(FIX_TCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) + (u32) (&__tcm_end - &__tcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 pool_size = (u32) (CONFIG_DTCM_NR_PAGES * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) - (u32) (&__tcm_end - &__dtcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 tcm_pool_start = __fix_to_virt(FIX_TCM - CONFIG_ITCM_NR_PAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) + (u32) (&__tcm_end - &__dtcm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tcm_pool = gen_pool_create(2, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = gen_pool_add(tcm_pool, tcm_pool_start, pool_size, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_err("%s: gen_pool add failed!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_info("%s: Added %d bytes @ 0x%08x to memory pool\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __func__, pool_size, tcm_pool_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int __init tcm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tcm_mapping_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tcm_setup_pool();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) arch_initcall(tcm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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