^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <asm/vmlinux.lds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) OUTPUT_ARCH(csky)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ENTRY(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __cskyBE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) jiffies = jiffies_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) jiffies = jiffies_64 + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VBR_BASE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) . = ALIGN(1024); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) vec_base = .; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) . += 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SECTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) . = PAGE_OFFSET + PHYS_OFFSET_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) _stext = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __init_begin = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) HEAD_TEXT_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) INIT_TEXT_SECTION(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) INIT_DATA_SECTION(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PERCPU_SECTION(L1_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __init_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .text : AT(ADDR(.text) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) _text = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) IRQENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SOFTIRQENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) TEXT_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SCHED_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CPUIDLE_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) LOCK_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) KPROBES_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *(.fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *(.gnu.warning)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) } = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) _etext = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* __init_begin __init_end must be page aligned for free_initmem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) _sdata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) RO_DATA(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) _edata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_HAVE_TCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .tcm_start : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __tcm_start = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .text_data_tcm FIXADDR_TCM : AT(__tcm_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) . = ALIGN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __stcm_text_data = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *(.tcm.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *(.tcm.rodata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifndef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *(.tcm.data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) . = ALIGN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __etcm_text_data = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) . = ADDR(.tcm_start) + SIZEOF(.tcm_start) + SIZEOF(.text_data_tcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_HAVE_DTCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ITCM_SIZE CONFIG_ITCM_NR_PAGES * PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .dtcm_start : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __dtcm_start = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .data_tcm FIXADDR_TCM + ITCM_SIZE : AT(__dtcm_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) . = ALIGN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __stcm_data = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *(.tcm.data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) . = ALIGN(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __etcm_data = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) . = ADDR(.dtcm_start) + SIZEOF(.data_tcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .tcm_end : AT(ADDR(.dtcm_start) + SIZEOF(.data_tcm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .tcm_end : AT(ADDR(.tcm_start) + SIZEOF(.text_data_tcm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __tcm_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) EXCEPTION_TABLE(L1_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, L1_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) VBR_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) _end = . ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) STABS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DWARF_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ELF_DETAILS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DISCARDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }