Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifndef __ASM_CSKY_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define __ASM_CSKY_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * I/O memory access primitives. Reads are ordered relative to any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * following Normal memory access. Writes are ordered relative to any prior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Normal memory access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * For CACHEV1 (807, 810), store instruction could fast retire, so we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * another mb() to prevent st fast retire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * For CACHEV2 (860), store instruction with PAGE_ATTR_NO_BUFFERABLE won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * fast retire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define readb(c)		({ u8  __v = readb_relaxed(c); rmb(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define readw(c)		({ u16 __v = readw_relaxed(c); rmb(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define readl(c)		({ u32 __v = readl_relaxed(c); rmb(); __v; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_CPU_HAS_CACHEV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define writeb(v,c)		({ wmb(); writeb_relaxed((v),(c)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define writew(v,c)		({ wmb(); writew_relaxed((v),(c)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define writel(v,c)		({ wmb(); writel_relaxed((v),(c)); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define writeb(v,c)		({ wmb(); writeb_relaxed((v),(c)); mb(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define writew(v,c)		({ wmb(); writew_relaxed((v),(c)); mb(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define writel(v,c)		({ wmb(); writel_relaxed((v),(c)); mb(); })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * I/O memory mapping functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ioremap_wc(addr, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	ioremap_prot((addr), (size), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		(_PAGE_IOREMAP & ~_CACHE_MASK) | _CACHE_UNCACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm-generic/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* __ASM_CSKY_IO_H */