Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Contributed by: Mark Salter (msalter@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/dscr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/special_insns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/timer64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct timer_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u32	reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u32	emumgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u32	reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u32	reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	u32	cntlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32	cnthi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u32	prdlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32	prdhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32	tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32	tgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32	wdtcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static struct timer_regs __iomem *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TCR_TSTATLO	     0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TCR_INVOUTPLO	     0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TCR_INVINPLO	     0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TCR_CPLO	     0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TCR_ENAMODELO_ONCE   0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TCR_ENAMODELO_CONT   0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TCR_ENAMODELO_MASK   0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TCR_PWIDLO_MASK      0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TCR_CLKSRCLO	     0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TCR_TIENLO	     0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TCR_TSTATHI	     (0x001 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TCR_INVOUTPHI	     (0x002 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TCR_CPHI	     (0x008 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TCR_PWIDHI_MASK      (0x030 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TCR_ENAMODEHI_ONCE   (0x040 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TCR_ENAMODEHI_CONT   (0x080 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TCR_ENAMODEHI_MASK   (0x0c0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TGCR_TIMLORS	     0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TGCR_TIMHIRS	     0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TGCR_TIMMODE_UD32    0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TGCR_TIMMODE_WDT64   0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TGCR_TIMMODE_CD32    0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TGCR_TIMMODE_MASK    0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TGCR_PSCHI_MASK      (0x00f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TGCR_TDDRHI_MASK     (0x00f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * Timer clocks are divided down from the CPU clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * The divisor is in the EMUMGTCLKSPD register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TIMER_DIVISOR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TIMER64_RATE (c6x_core_freq / TIMER_DIVISOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TIMER64_MODE_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TIMER64_MODE_ONE_SHOT TCR_ENAMODELO_ONCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TIMER64_MODE_PERIODIC TCR_ENAMODELO_CONT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int timer64_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static int timer64_devstate_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static void timer64_config(unsigned long period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	soc_writel(tcr, &timer->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	soc_writel(period - 1, &timer->prdlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	soc_writel(0, &timer->cntlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	tcr |= timer64_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	soc_writel(tcr, &timer->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void timer64_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (timer64_devstate_id >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* disable timer, reset count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	soc_writel(0, &timer->prdlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* use internal clock and 1 cycle pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	val = soc_readl(&timer->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	soc_writel(val & ~(TCR_CLKSRCLO | TCR_PWIDLO_MASK), &timer->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* dual 32-bit unchained mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	val = soc_readl(&timer->tgcr) & ~TGCR_TIMMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	soc_writel(val, &timer->tgcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	soc_writel(val | (TGCR_TIMLORS | TGCR_TIMMODE_UD32), &timer->tgcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void timer64_disable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* disable timer, reset count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	soc_writel(0, &timer->prdlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (timer64_devstate_id >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		      struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	timer64_config(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	timer64_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	timer64_mode = TIMER64_MODE_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	timer64_config(TIMER64_RATE / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	timer64_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	timer64_mode = TIMER64_MODE_ONE_SHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	timer64_mode = TIMER64_MODE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	timer64_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct clock_event_device t64_clockevent_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.name			= "TIMER64_EVT32_TIMER",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.features		= CLOCK_EVT_FEAT_ONESHOT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				  CLOCK_EVT_FEAT_PERIODIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.rating			= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.set_state_shutdown	= shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.set_state_periodic	= set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.set_state_oneshot	= set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.set_next_event		= next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static irqreturn_t timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct clock_event_device *cd = &t64_clockevent_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	cd->event_handler(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __init timer64_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct clock_event_device *cd = &t64_clockevent_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct device_node *np, *first = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int err, found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	for_each_compatible_node(np, NULL, "ti,c64x+timer64") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		err = of_property_read_u32(np, "ti,core-mask", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			if (val & (1 << get_coreid())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		} else if (!first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			first = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/* try first one with no core-mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			np = of_node_get(first);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			pr_debug("Cannot find ti,c64x+timer64 timer.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	timer = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (!timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		pr_debug("%pOF: Cannot map timer registers.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	pr_debug("%pOF: Timer registers=%p.\n", np, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	cd->irq	= irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (cd->irq == NO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		pr_debug("%pOF: Cannot find interrupt.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		iounmap(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* If there is a device state control, save the ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		timer64_devstate_id = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		 * It is necessary to enable the timer block here because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		 * the TIMER_DIVISOR macro needs to read a timer register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		 * to get the divisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	pr_debug("%pOF: Timer irq=%d.\n", np, cd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	cd->max_delta_ns	= clockevent_delta2ns(0x7fffffff, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	cd->max_delta_ticks	= 0x7fffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	cd->min_delta_ns	= clockevent_delta2ns(250, cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	cd->min_delta_ticks	= 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	cd->cpumask		= cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	clockevents_register_device(cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (request_irq(cd->irq, timer_interrupt, IRQF_TIMER, "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			&t64_clockevent_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		pr_err("Failed to request irq %d (timer)\n", cd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }