^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mark Salter <msalter@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/special_insns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Common SoC clock support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Default input for PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk clkin1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = "clkin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .node = LIST_HEAD_INIT(clkin1.node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .children = LIST_HEAD_INIT(clkin1.children),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .childnode = LIST_HEAD_INIT(clkin1.childnode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pll_data c6x_soc_pll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .sysclks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = "pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .parent = &clkin1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .pll_data = &c6x_soc_pll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .name = "pll1_sysclk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "pll1_sysclk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .name = "pll1_sysclk3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "pll1_sysclk4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "pll1_sysclk5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .name = "pll1_sysclk6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "pll1_sysclk7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = "pll1_sysclk8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .name = "pll1_sysclk9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "pll1_sysclk10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .name = "pll1_sysclk11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "pll1_sysclk12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "pll1_sysclk13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "pll1_sysclk14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "pll1_sysclk15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "pll1_sysclk16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .parent = &c6x_soc_pll1.sysclks[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .flags = CLK_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* CPU core clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk c6x_core_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* miscellaneous IO clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct clk c6x_i2c_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk c6x_watchdog_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct clk c6x_mcbsp1_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "mcbsp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk c6x_mcbsp2_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "mcbsp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk c6x_mdio_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #ifdef CONFIG_SOC_TMS320C6455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct clk_lookup c6455_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLK(NULL, "core", &c6x_core_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CLK("watchdog", NULL, &c6x_watchdog_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CLK("", NULL, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __init c6455_setup_clocks(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pll_data *pll = &c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct clk *sysclks = pll->sysclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pll->flags = PLL_HAS_PRE | PLL_HAS_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sysclks[2].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sysclks[2].div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sysclks[3].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sysclks[3].div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) sysclks[4].div = PLLDIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sysclks[5].div = PLLDIV5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) c6x_core_clk.parent = &sysclks[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) c6x_i2c_clk.parent = &sysclks[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) c6x_watchdog_clk.parent = &sysclks[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) c6x_mdio_clk.parent = &sysclks[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) c6x_clks_init(c6455_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif /* CONFIG_SOC_TMS320C6455 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef CONFIG_SOC_TMS320C6457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct clk_lookup c6457_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLK(NULL, "core", &c6x_core_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CLK("watchdog", NULL, &c6x_watchdog_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CLK("", NULL, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void __init c6457_setup_clocks(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct pll_data *pll = &c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clk *sysclks = pll->sysclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pll->flags = PLL_HAS_MUL | PLL_HAS_POST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sysclks[1].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sysclks[1].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sysclks[2].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sysclks[2].div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sysclks[3].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sysclks[3].div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sysclks[4].div = PLLDIV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sysclks[5].div = PLLDIV5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) c6x_core_clk.parent = &sysclks[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) c6x_i2c_clk.parent = &sysclks[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) c6x_watchdog_clk.parent = &sysclks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) c6x_mdio_clk.parent = &sysclks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) c6x_clks_init(c6457_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif /* CONFIG_SOC_TMS320C6455 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_SOC_TMS320C6472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct clk_lookup c6472_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CLK(NULL, "core", &c6x_core_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CLK("watchdog", NULL, &c6x_watchdog_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) CLK("", NULL, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* assumptions used for delay loop calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MIN_CLKIN1_KHz 15625
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MAX_CORE_KHz 700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MIN_PLLOUT_KHz MIN_CLKIN1_KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void __init c6472_setup_clocks(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct pll_data *pll = &c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct clk *sysclks = pll->sysclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pll->flags = PLL_HAS_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 1; i <= 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sysclks[i].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sysclks[i].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sysclks[7].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sysclks[7].div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sysclks[8].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sysclks[8].div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sysclks[9].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sysclks[9].div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sysclks[10].div = PLLDIV10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) c6x_core_clk.parent = &sysclks[get_coreid() + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) c6x_i2c_clk.parent = &sysclks[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) c6x_watchdog_clk.parent = &sysclks[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) c6x_mdio_clk.parent = &sysclks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) c6x_clks_init(c6472_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif /* CONFIG_SOC_TMS320C6472 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #ifdef CONFIG_SOC_TMS320C6474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct clk_lookup c6474_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) CLK(NULL, "core", &c6x_core_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CLK("watchdog", NULL, &c6x_watchdog_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK("", NULL, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void __init c6474_setup_clocks(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct pll_data *pll = &c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct clk *sysclks = pll->sysclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pll->flags = PLL_HAS_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sysclks[7].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) sysclks[7].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) sysclks[9].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sysclks[9].div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) sysclks[10].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) sysclks[10].div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) sysclks[11].div = PLLDIV11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) sysclks[12].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) sysclks[12].div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) sysclks[13].div = PLLDIV13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) c6x_core_clk.parent = &sysclks[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) c6x_i2c_clk.parent = &sysclks[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) c6x_watchdog_clk.parent = &sysclks[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) c6x_mcbsp1_clk.parent = &sysclks[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) c6x_mcbsp2_clk.parent = &sysclks[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) c6x_clks_init(c6474_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif /* CONFIG_SOC_TMS320C6474 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #ifdef CONFIG_SOC_TMS320C6678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct clk_lookup c6678_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CLK(NULL, "core", &c6x_core_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CLK("", NULL, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void __init c6678_setup_clocks(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct pll_data *pll = &c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct clk *sysclks = pll->sysclks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pll->flags = PLL_HAS_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sysclks[1].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sysclks[1].div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) sysclks[2].div = PLLDIV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) sysclks[3].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sysclks[3].div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) sysclks[4].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sysclks[4].div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sysclks[5].div = PLLDIV5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sysclks[6].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sysclks[6].div = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sysclks[7].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sysclks[7].div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) sysclks[8].div = PLLDIV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sysclks[9].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sysclks[9].div = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) sysclks[10].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) sysclks[10].div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sysclks[11].flags |= FIXED_DIV_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sysclks[11].div = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) c6x_core_clk.parent = &sysclks[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) c6x_i2c_clk.parent = &sysclks[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) c6x_clks_init(c6678_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif /* CONFIG_SOC_TMS320C6678 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct of_device_id c6x_clkc_match[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #ifdef CONFIG_SOC_TMS320C6455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #ifdef CONFIG_SOC_TMS320C6457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { .compatible = "ti,c6457-pll", .data = c6457_setup_clocks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #ifdef CONFIG_SOC_TMS320C6472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { .compatible = "ti,c6472-pll", .data = c6472_setup_clocks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef CONFIG_SOC_TMS320C6474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #ifdef CONFIG_SOC_TMS320C6678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .compatible = "ti,c64x+pll" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void __init c64x_setup_clocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void (*__setup_clocks)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct pll_data *pll = &c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) node = of_find_matching_node(NULL, c6x_clkc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pll->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!pll->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) err = of_property_read_u32(node, "clock-frequency", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (err || val == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pr_err("%pOF: no clock-frequency found! Using %dMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) node, (int)val / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val = 25000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clkin1.rate = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pll->bypass_delay = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val = 30000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pll->reset_delay = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val = 30000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pll->lock_delay = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* id->data is a pointer to SoC-specific setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) id = of_match_node(c6x_clkc_match, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (id && id->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __setup_clocks = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) __setup_clocks(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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