Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Clock and PLL control for C64x+ devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010, 2011 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Contributed by: Mark Salter <msalter@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copied heavily from arm/mach-davinci/clock.c, so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2006-2007 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2008-2009 Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static LIST_HEAD(clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static DEFINE_MUTEX(clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static DEFINE_SPINLOCK(clockfw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static void __clk_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	if (clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		__clk_enable(clk->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	clk->usecount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void __clk_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	if (WARN_ON(clk->usecount == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	--clk->usecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	if (clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		__clk_disable(clk->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) int clk_enable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	spin_lock_irqsave(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	__clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spin_unlock_irqrestore(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) EXPORT_SYMBOL(clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) void clk_disable(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	spin_lock_irqsave(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	__clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	spin_unlock_irqrestore(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) EXPORT_SYMBOL(clk_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) unsigned long clk_get_rate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) EXPORT_SYMBOL(clk_get_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) long clk_round_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (clk->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return clk->round_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) EXPORT_SYMBOL(clk_round_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* Propagate rate to children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void propagate_rate(struct clk *root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	list_for_each_entry(clk, &root->children, childnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if (clk->recalc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			clk->rate = clk->recalc(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		propagate_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int clk_set_rate(struct clk *clk, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (clk->set_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		ret = clk->set_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	spin_lock_irqsave(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (clk->recalc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			clk->rate = clk->recalc(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		propagate_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	spin_unlock_irqrestore(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL(clk_set_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int clk_set_parent(struct clk *clk, struct clk *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* Cannot change parent on enabled clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (WARN_ON(clk->usecount))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mutex_lock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	clk->parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	list_del_init(&clk->childnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	list_add(&clk->childnode, &clk->parent->children);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mutex_unlock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	spin_lock_irqsave(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (clk->recalc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		clk->rate = clk->recalc(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	propagate_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	spin_unlock_irqrestore(&clockfw_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL(clk_set_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int clk_register(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (WARN(clk->parent && !clk->parent->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		 "CLK: %s parent %s has no rate!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		 clk->name, clk->parent->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	mutex_lock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	list_add_tail(&clk->node, &clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		list_add_tail(&clk->childnode, &clk->parent->children);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	mutex_unlock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* If rate is already set, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (clk->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Else, see if there is a way to calculate it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (clk->recalc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		clk->rate = clk->recalc(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Otherwise, default to parent rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	else if (clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		clk->rate = clk->parent->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) EXPORT_SYMBOL(clk_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void clk_unregister(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (clk == NULL || IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	mutex_lock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	list_del(&clk->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	list_del(&clk->childnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mutex_unlock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EXPORT_SYMBOL(clk_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static u32 pll_read(struct pll_data *pll, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return soc_readl(pll->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static unsigned long clk_sysclk_recalc(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 v, plldiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct pll_data *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	unsigned long rate = clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (WARN_ON(!clk->parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	rate = clk->parent->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* the parent must be a PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (WARN_ON(!clk->parent->pll_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	pll = clk->parent->pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* If pre-PLL, source clock is before the multiplier and divider(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (clk->flags & PRE_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		rate = pll->input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!clk->div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		pr_debug("%s: (no divider) rate = %lu KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			 clk->name, rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (clk->flags & FIXED_DIV_PLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		rate /= clk->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		pr_debug("%s: (fixed divide by %d) rate = %lu KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			 clk->name, clk->div, rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	v = pll_read(pll, clk->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (v & PLLDIV_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		plldiv = (v & PLLDIV_RATIO_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (plldiv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		plldiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	rate /= plldiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	pr_debug("%s: (divide by %d) rate = %lu KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		 clk->name, plldiv, rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static unsigned long clk_leafclk_recalc(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (WARN_ON(!clk->parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	pr_debug("%s: (parent %s) rate = %lu KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		 clk->name, clk->parent->name,	clk->parent->rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return clk->parent->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static unsigned long clk_pllclk_recalc(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u32 ctrl, mult = 0, prediv = 0, postdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u8 bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct pll_data *pll = clk->pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	unsigned long rate = clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (clk->flags & FIXED_RATE_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ctrl = pll_read(pll, PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	rate = pll->input_rate = clk->parent->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ctrl & PLLCTL_PLLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		bypass = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		bypass = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (pll->flags & PLL_HAS_MUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		mult = pll_read(pll, PLLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		mult = (mult & PLLM_PLLM_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (pll->flags & PLL_HAS_PRE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		prediv = pll_read(pll, PLLPRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (prediv & PLLDIV_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			prediv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (pll->flags & PLL_HAS_POST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		postdiv = pll_read(pll, PLLPOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (postdiv & PLLDIV_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			postdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (prediv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			rate /= prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		if (mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			rate *= mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		if (postdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			rate /= postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		pr_debug("PLL%d: input = %luMHz, pre[%d] mul[%d] post[%d] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			 "--> %luMHz output.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			 pll->num, clk->parent->rate / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			 prediv, mult, postdiv, rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		pr_debug("PLL%d: input = %luMHz, bypass mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			 pll->num, clk->parent->rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void __init __init_clk(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	INIT_LIST_HEAD(&clk->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	INIT_LIST_HEAD(&clk->children);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	INIT_LIST_HEAD(&clk->childnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (!clk->recalc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		/* Check if clock is a PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		if (clk->pll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			clk->recalc = clk_pllclk_recalc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		/* Else, if it is a PLL-derived clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		else if (clk->flags & CLK_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			clk->recalc = clk_sysclk_recalc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		/* Otherwise, it is a leaf clock (PSC clock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		else if (clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			clk->recalc = clk_leafclk_recalc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __init c6x_clks_init(struct clk_lookup *clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct clk_lookup *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	size_t num_clocks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	for (c = clocks; c->clk; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		clk = c->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		__init_clk(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		clk_register(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		num_clocks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		/* Turn on clocks that Linux doesn't otherwise manage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (clk->flags & ALWAYS_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	clkdev_add_table(clocks, num_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CLKNAME_MAX	10		/* longest clock name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define NEST_DELTA	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define NEST_MAX	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	char		*state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	char		buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct clk	*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	unsigned	i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (parent->flags & CLK_PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		state = "pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		state = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	/* <nest spaces> name <pad to end> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	memset(buf, ' ', sizeof(buf) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	buf[sizeof(buf) - 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	i = strlen(parent->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	memcpy(buf + nest, parent->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	       min(i, (unsigned)(sizeof(buf) - 1 - nest)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		   buf, parent->usecount, state, clk_get_rate(parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* REVISIT show device associations too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/* cost is now small, but not linear... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	list_for_each_entry(clk, &parent->children, childnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dump_clock(s, nest + NEST_DELTA, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int c6x_ck_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	mutex_lock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	list_for_each_entry(clk, &clocks, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		if (!clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			dump_clock(m, 0, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	mutex_unlock(&clocks_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int c6x_ck_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return single_open(file, c6x_ck_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct file_operations c6x_ck_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.open		= c6x_ck_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	.read		= seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	.llseek		= seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.release	= single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int __init c6x_clk_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	debugfs_create_file("c6x_clocks", S_IFREG | S_IRUGO, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 			    &c6x_ck_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) device_initcall(c6x_clk_debugfs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #endif /* CONFIG_DEBUG_FS */