Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Support for C64x+ Megamodule Interrupt Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2010, 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Contributed by: Mark Salter <msalter@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/megamod-pic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define NR_COMBINERS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define NR_MUX_OUTPUTS  12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IRQ_UNMAPPED 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Megamodule Interrupt Controller register layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct megamod_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32	evtflag[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32	evtset[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32	evtclr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32	reserved0[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32	evtmask[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32	mevtflag[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32	expmask[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32	mexpflag[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32	intmux_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32	intmux[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32	reserved1[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32	aegmux[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32	reserved2[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32	intxstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32	intxclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32	intdmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32	reserved3[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32	evtasrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct megamod_pic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct irq_domain *irqhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct megamod_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* hw mux mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int output_to_irq[NR_MUX_OUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct megamod_pic *mm_pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct megamod_cascade_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct megamod_pic *pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static struct megamod_cascade_data cascade_data[NR_COMBINERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void mask_megamod(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct megamod_pic *pic = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	irq_hw_number_t src = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	raw_spin_lock(&pic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	soc_writel(soc_readl(evtmask) | (1 << (src & 31)), evtmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	raw_spin_unlock(&pic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static void unmask_megamod(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct megamod_pic *pic = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	irq_hw_number_t src = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 __iomem *evtmask = &pic->regs->evtmask[src / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	raw_spin_lock(&pic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	soc_writel(soc_readl(evtmask) & ~(1 << (src & 31)), evtmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	raw_spin_unlock(&pic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static struct irq_chip megamod_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.name		= "megamod",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.irq_mask	= mask_megamod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.irq_unmask	= unmask_megamod,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void megamod_irq_cascade(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct megamod_cascade_data *cascade;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct megamod_pic *pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int n, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	cascade = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	pic = cascade->pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	idx = cascade->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		n = __ffs(events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		irq = irq_linear_revmap(pic->irqhost, idx * 32 + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		soc_writel(1 << n, &pic->regs->evtclr[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int megamod_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		       irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct megamod_pic *pic = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* We shouldn't see a hwirq which is muxed to core controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	for (i = 0; i < NR_MUX_OUTPUTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (pic->output_to_irq[i] == hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	irq_set_chip_data(virq, pic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	irq_set_chip_and_handler(virq, &megamod_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Set default irq type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	irq_set_irq_type(virq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct irq_domain_ops megamod_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.map	= megamod_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.xlate	= irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void __init set_megamod_mux(struct megamod_pic *pic, int src, int output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int index, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (src < 0 || src >= (NR_COMBINERS * 32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		pic->output_to_irq[output] = IRQ_UNMAPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* four mappings per mux register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	index = output / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	offset = (output & 3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	val = soc_readl(&pic->regs->intmux[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	val &= ~(0xff << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	val |= src << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	soc_writel(val, &pic->regs->intmux[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * Parse the MUX mapping, if one exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * The MUX map is an array of up to 12 cells; one for each usable core priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * interrupt. The value of a given cell is the megamodule interrupt source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * which is to me MUXed to the output corresponding to the cell position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * withing the array. The first cell in the array corresponds to priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * 4 and the last (12th) cell corresponds to priority 15. The allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * sources (0 - 3) are not allowed to be mapped through this property. They
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * are handled through the "interrupts" property. This allows us to use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * value of zero as a "do not map" placeholder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void __init parse_priority_map(struct megamod_pic *pic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				      int *mapping, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct device_node *np = irq_domain_get_of_node(pic->irqhost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	const __be32 *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int i, maplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		maplen /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (maplen > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			maplen = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		for (i = 0; i < maplen; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			val = be32_to_cpup(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			if (val && val >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				mapping[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			++map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct megamod_pic * __init init_megamod_pic(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct megamod_pic *pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int i, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int mapping[NR_MUX_OUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	pr_info("Initializing C64x+ Megamodule PIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	pic = kzalloc(sizeof(struct megamod_pic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!pic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		pr_err("%pOF: Could not alloc PIC structure.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	pic->irqhost = irq_domain_add_linear(np, NR_COMBINERS * 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 					     &megamod_domain_ops, pic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (!pic->irqhost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		pr_err("%pOF: Could not alloc host.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		goto error_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	pic->irqhost->host_data = pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	raw_spin_lock_init(&pic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	pic->regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (!pic->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		pr_err("%pOF: Could not map registers.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		goto error_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* Initialize MUX map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	for (i = 0; i < ARRAY_SIZE(mapping); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		mapping[i] = IRQ_UNMAPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	parse_priority_map(pic, mapping, ARRAY_SIZE(mapping));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * We can have up to 12 interrupts cascading to the core controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * These cascades can be from the combined interrupt sources or for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * individual interrupt sources. The "interrupts" property only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * deals with the cascaded combined interrupts. The individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * interrupts muxed to the core controller use the core controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * as their interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	for (i = 0; i < NR_COMBINERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		irq = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		if (irq == NO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		irq_data = irq_get_irq_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (!irq_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			pr_err("%pOF: combiner-%d no irq_data for virq %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			       np, i, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		hwirq = irq_data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		 * Check that device tree provided something in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		 * of the core priority interrupts (4 - 15).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		if (hwirq < 4 || hwirq >= NR_PRIORITY_IRQS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			pr_err("%pOF: combiner-%d core irq %ld out of range!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			       np, i, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		/* record the mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		mapping[hwirq - 4] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		pr_debug("%pOF: combiner-%d cascading to hwirq %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			 np, i, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		cascade_data[i].pic = pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		cascade_data[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		/* mask and clear all events in combiner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		soc_writel(~0, &pic->regs->evtmask[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		soc_writel(~0, &pic->regs->evtclr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		irq_set_chained_handler_and_data(irq, megamod_irq_cascade,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 						 &cascade_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Finally, set up the MUX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	for (i = 0; i < NR_MUX_OUTPUTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (mapping[i] != IRQ_UNMAPPED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			pr_debug("%pOF: setting mux %d to priority %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				 np, mapping[i], i + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			set_megamod_mux(pic, mapping[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return pic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) error_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	kfree(pic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  * Return next active event after ACK'ing it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  * Return -1 if no events active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int get_exception(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int i, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	for (i = 0; i < NR_COMBINERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		mask = soc_readl(&mm_pic->regs->mexpflag[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			bit = __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			soc_writel(1 << bit, &mm_pic->regs->evtclr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			return (i * 32) + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void assert_event(unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	soc_writel(val, &mm_pic->regs->evtasrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void __init megamod_pic_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	mm_pic = init_megamod_pic(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	soc_ops.get_exception = get_exception;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	soc_ops.assert_event = assert_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }