Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  External Memory Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Author: Mark Salter <msalter@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/dscr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NUM_EMIFA_CHIP_ENABLES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct emifa_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	u32	midr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u32	stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	u32	reserved1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	u32	bprio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u32	reserved2[23];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u32	cecfg[NUM_EMIFA_CHIP_ENABLES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32	reserved3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32	awcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u32	reserved4[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u32	intraw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u32	intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u32	intmskset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u32	intmskclr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct of_device_id emifa_match[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	{ .compatible = "ti,c64x+emifa"	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * Parse device tree for existence of an EMIF (External Memory Interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * and initialize it if found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int __init c6x_emifa_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	struct emifa_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	int i, len, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	node = of_find_matching_node(NULL, emifa_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	regs = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	/* look for a dscr-based enable for emifa pin buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	err = of_property_read_u32_array(node, "ti,dscr-dev-enable", &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		dscr_set_devstate(val, DSCR_DEVSTATE_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	/* set up the chip enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	p = of_get_property(node, "ti,emifa-ce-config", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		len /= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		if (len > NUM_EMIFA_CHIP_ENABLES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			len = NUM_EMIFA_CHIP_ENABLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		for (i = 0; i <= len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			soc_writel(be32_to_cpup(&p[i]), &regs->cecfg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	err = of_property_read_u32_array(node, "ti,emifa-burst-priority", &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		soc_writel(val, &regs->bprio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	err = of_property_read_u32_array(node, "ti,emifa-async-wait-control", &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		soc_writel(val, &regs->awcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pure_initcall(c6x_emifa_init);