^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Device State Control Registers driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mark Salter <msalter@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The Device State Control Registers (DSCR) provide SoC level control over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * a number of peripherals. Details vary considerably among the various SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * parts. In general, the DSCR block will provide one or more configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * registers often protected by a lock register. One or more key values must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * be written to a lock register in order to unlock the configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The configuration register may be used to enable (and disable in some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * cases) SoC pin drivers, peripheral clock sources (internal or pin), etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * In some cases, a configuration register is write once or the individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * bits are write once. That is, you may be able to enable a device, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * will not be able to disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * In addition to device configuration, the DSCR block may provide registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * which are used to reset SoC peripherals, provide device ID information,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * provide MAC addresses, and other miscellaneous functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/dscr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX_DEVSTATE_IDS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_DEVCTL_REGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MAX_DEVSTAT_REGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_LOCKED_REGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX_SOC_EMACS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct rmii_reset_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Some registerd may be locked. In order to write to these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * registers, the key value must first be written to the lockreg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct locked_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 reg; /* offset from base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 lockreg; /* offset from base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 key; /* unlock key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * This describes a contiguous area of like control bits used to enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * SoC devices. Each controllable device is given an ID which is used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * individual device drivers to control the device state. These IDs start at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * zero and are assigned sequentially to the control bitfield ranges described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * by this structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct devstate_ctl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 reg; /* register holding the control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 start_id; /* start id of this range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 num_ids; /* number of devices in this range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 enable_only; /* bits are write-once to enable only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 enable; /* value used to enable device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 disable; /* value used to disable device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 shift; /* starting (rightmost) bit in range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 nbits; /* number of bits per device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * This describes a region of status bits indicating the state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * various devices. This is used internally to wait for status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * change completion when enabling/disabling a device. Status is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * optional and not all device controls will have a corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct devstate_stat_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 reg; /* register holding the status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 start_id; /* start id of this range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 num_ids; /* number of devices in this range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 enable; /* value indicating enabled state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 disable; /* value indicating disabled state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 shift; /* starting (rightmost) bit in range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 nbits; /* number of bits per device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct devstate_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct devstate_ctl_reg *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct devstate_stat_reg *stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* These are callbacks to SOC-specific code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct dscr_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void (*init)(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct dscr_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 kick_reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 kick_key[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct locked_reg locked[MAX_LOCKED_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct devstate_info devstate_info[MAX_DEVSTATE_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct rmii_reset_reg rmii_resets[MAX_SOC_EMACS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct dscr_regs dscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct locked_reg *find_locked_reg(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (i = 0; i < MAX_LOCKED_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (dscr.locked[i].key && reg == dscr.locked[i].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return &dscr.locked[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Write to a register with one lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void dscr_write_locked1(u32 reg, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 lock, u32 key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __iomem *reg_addr = dscr.base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void __iomem *lock_addr = dscr.base + lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * For some registers, the lock is relocked after a short number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * of cycles. We have to put the lock write and register write in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * the same fetch packet to meet this timing. The .align ensures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * the two stw instructions are in the same fetch packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) asm volatile ("b .s2 0f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "nop 5\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) " .align 5\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "0:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "stw .D1T2 %3,*%2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "stw .D1T2 %1,*%0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* in case the hw doesn't reset the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) soc_writel(0, lock_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Write to a register protected by two lock registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void dscr_write_locked2(u32 reg, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 lock0, u32 key0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 lock1, u32 key1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) soc_writel(key0, dscr.base + lock0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) soc_writel(key1, dscr.base + lock1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) soc_writel(val, dscr.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) soc_writel(0, dscr.base + lock0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) soc_writel(0, dscr.base + lock1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void dscr_write(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct locked_reg *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) lock = find_locked_reg(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dscr_write_locked1(reg, val, lock->lockreg, lock->key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else if (dscr.kick_key[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dscr.kick_reg[1], dscr.kick_key[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) soc_writel(val, dscr.base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Drivers can use this interface to enable/disable SoC IP blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void dscr_set_devstate(int id, enum dscr_devstate_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct devstate_ctl_reg *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct devstate_stat_reg *stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct devstate_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 ctl_val, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int ctl_shift, ctl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!dscr.base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (id < 0 || id >= MAX_DEVSTATE_IDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) info = &dscr.devstate_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ctl = info->ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) stat = info->stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ctl == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case DSCR_DEVSTATE_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ctl_val = ctl->enable << ctl_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case DSCR_DEVSTATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ctl->enable_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ctl_val = ctl->disable << ctl_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_lock_irqsave(&dscr.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val = soc_readl(dscr.base + ctl->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val &= ~ctl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val |= ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dscr_write(ctl->reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spin_unlock_irqrestore(&dscr.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (state == DSCR_DEVSTATE_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ctl_val = stat->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ctl_val = stat->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = soc_readl(dscr.base + stat->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val >>= ctl_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val &= ((1 << stat->nbits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } while (val != ctl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) EXPORT_SYMBOL(dscr_set_devstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Drivers can use this to reset RMII module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void dscr_rmii_reset(int id, int assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct rmii_reset_reg *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (id < 0 || id >= MAX_SOC_EMACS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) r = &dscr.rmii_resets[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (r->mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_lock_irqsave(&dscr.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val = soc_readl(dscr.base + r->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (assert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dscr_write(r->reg, val | r->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dscr_write(r->reg, val & ~(r->mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_unlock_irqrestore(&dscr.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) EXPORT_SYMBOL(dscr_rmii_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void __init dscr_parse_devstat(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) c6x_devstat = soc_readl(base + val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) printk(KERN_INFO "DEVSTAT: %08x\n", c6x_devstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void __init dscr_parse_silicon_rev(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 vals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) c6x_silicon_rev = soc_readl(base + vals[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) c6x_silicon_rev >>= vals[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) c6x_silicon_rev &= vals[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Some SoCs will have a pair of fuse registers which hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * an ethernet MAC address. The "ti,dscr-mac-fuse-regs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * property is a mapping from fuse register bytes to MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * address bytes. The expected format is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * ti,dscr-mac-fuse-regs = <reg0 b3 b2 b1 b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * reg1 b3 b2 b1 b0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * reg0 and reg1 are the offsets of the two fuse registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * b3-b0 positionally represent bytes within the fuse register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * b3 is the most significant byte and b0 is the least.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Allowable values for b3-b0 are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * 0 = fuse register byte not used in MAC address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * 1-6 = index+1 into c6x_fuse_mac[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void __init dscr_parse_mac_fuse(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 vals[10], fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int f, i, j, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) vals, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (f = 0; f < 2; f++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) fuse = soc_readl(base + vals[f * 5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (vals[j] && vals[j] <= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) c6x_fuse_mac[vals[j] - 1] = fuse >> i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void __init dscr_parse_rmii_resets(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int i, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* look for RMII reset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) p = of_get_property(node, "ti,dscr-rmii-resets", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* parse all the reg/mask pairs we can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) size /= (sizeof(*p) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (size > MAX_SOC_EMACS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) size = MAX_SOC_EMACS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dscr.rmii_resets[i].reg = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dscr.rmii_resets[i].mask = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void __init dscr_parse_privperm(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 vals[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dscr_write(vals[0], vals[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * SoCs may have "locked" DSCR registers which can only be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * to only after writing a key value to a lock registers. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * regisers can be described with the "ti,dscr-locked-regs" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * This property provides a list of register descriptions with each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * description consisting of three values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * ti,dscr-locked-regs = <reg0 lockreg0 key0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * regN lockregN keyN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * reg is the offset of the locked register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * lockreg is the offset of the lock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * key is the unlock key written to lockreg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void __init dscr_parse_locked_regs(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct locked_reg *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int i, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) p = of_get_property(node, "ti,dscr-locked-regs", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* parse all the register descriptions we can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) size /= (sizeof(*p) * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (size > MAX_LOCKED_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) size = MAX_LOCKED_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) r = &dscr.locked[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) r->reg = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) r->lockreg = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) r->key = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * SoCs may have DSCR registers which are only write enabled after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * writing specific key values to two registers. The two key registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * and the key values can be parsed from a "ti,dscr-kick-regs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * propety with the following layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * ti,dscr-kick-regs = <kickreg0 key0 kickreg1 key1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * kickreg is the offset of the "kick" register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * key is the value which unlocks writing for protected regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void __init dscr_parse_kick_regs(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 vals[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dscr.kick_reg[0] = vals[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dscr.kick_key[0] = vals[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dscr.kick_reg[1] = vals[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dscr.kick_key[1] = vals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * SoCs may provide controls to enable/disable individual IP blocks. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * controls in the DSCR usually control pin drivers but also may control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * clocking and or resets. The device tree is used to describe the bitfields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * in registers used to control device state. The number of bits and their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * values may vary even within the same register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * The layout of these bitfields is described by the ti,dscr-devstate-ctl-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * property. This property is a list where each element describes a contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * range of control fields with like properties. Each element of the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * consists of 7 cells with the following values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * start_id num_ids reg enable disable start_bit nbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * start_id is device id for the first device control in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * num_ids is the number of device controls in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * reg is the offset of the register holding the control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * enable is the value to enable a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * disable is the value to disable a device (0xffffffff if cannot disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * start_bit is the bit number of the first bit in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * nbits is the number of bits per device control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void __init dscr_parse_devstate_ctl_regs(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct devstate_ctl_reg *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int i, j, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* parse all the ranges we can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) size /= (sizeof(*p) * 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (size > MAX_DEVCTL_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) size = MAX_DEVCTL_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) r = &dscr.devctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) r->start_id = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) r->num_ids = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) r->reg = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) r->enable = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) r->disable = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (r->disable == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) r->enable_only = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) r->shift = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) r->nbits = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) for (j = r->start_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) j < (r->start_id + r->num_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dscr.devstate_info[j].ctl = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * SoCs may provide status registers indicating the state (enabled/disabled) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * devices on the SoC. The device tree is used to describe the bitfields in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * registers used to provide device status. The number of bits and their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * values used to provide status may vary even within the same register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * The layout of these bitfields is described by the ti,dscr-devstate-stat-regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * property. This property is a list where each element describes a contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * range of status fields with like properties. Each element of the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * consists of 7 cells with the following values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * start_id num_ids reg enable disable start_bit nbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * start_id is device id for the first device status in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * num_ids is the number of devices covered by the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * reg is the offset of the register holding the status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * enable is the value indicating device is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * disable is the value indicating device is disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * start_bit is the bit number of the first bit in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * nbits is the number of bits per device status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void __init dscr_parse_devstate_stat_regs(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct devstate_stat_reg *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int i, j, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* parse all the ranges we can handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) size /= (sizeof(*p) * 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (size > MAX_DEVSTAT_REGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) size = MAX_DEVSTAT_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) r = &dscr.devstat[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) r->start_id = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) r->num_ids = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) r->reg = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) r->enable = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) r->disable = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) r->shift = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) r->nbits = be32_to_cpup(p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (j = r->start_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) j < (r->start_id + r->num_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dscr.devstate_info[j].stat = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct of_device_id dscr_ids[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { .compatible = "ti,c64x+dscr" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Probe for DSCR area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * This has to be done early on in case timer or interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * needs something. e.g. On C6455 SoC, timer must be enabled through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * DSCR before it is functional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) void __init dscr_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_lock_init(&dscr.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) node = of_find_matching_node(NULL, dscr_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dscr.base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dscr_parse_devstat(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dscr_parse_silicon_rev(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dscr_parse_mac_fuse(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dscr_parse_rmii_resets(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dscr_parse_locked_regs(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dscr_parse_kick_regs(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dscr_parse_devstate_ctl_regs(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dscr_parse_devstate_stat_regs(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dscr_parse_privperm(node, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags