Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ; SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ;  Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) ;  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) ;  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) ;  This section handles all the interrupt vector routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) ;  At RESET the processor sets up the DRAM timing parameters and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) ;  branches to the label _c_int00 which handles initialization for the C code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ALIGNMENT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	.macro IRQVEC name, handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.align ALIGNMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.hidden \name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	.global \name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) \name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_C6X_BIG_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	STW	.D2T1	A0,*B15--[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  ||	MVKL	.S1	\handler,A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	MVKH	.S1	\handler,A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	B	.S2X	A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	LDW	.D2T1	*++B15[2],A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	NOP	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #else /* CONFIG_C6X_BIG_KERNEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	B	.S2	\handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	.endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif /* CONFIG_C6X_BIG_KERNEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	   .sect ".vectors","ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	   .align ALIGNMENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	   .global RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	   .hidden RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef CONFIG_C6X_BIG_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	   MVKL	.S1	_c_int00,A0		; branch to _c_int00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	   MVKH	.S1	_c_int00,A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	   B	.S2X	A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	   B	.S2	_c_int00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	   NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	   IRQVEC NMI,_nmi_handler		; NMI interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	   IRQVEC AINT,_bad_interrupt		; reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	   IRQVEC MSGINT,_bad_interrupt		; reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	   IRQVEC INT4,_int4_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	   IRQVEC INT5,_int5_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	   IRQVEC INT6,_int6_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	   IRQVEC INT7,_int7_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	   IRQVEC INT8,_int8_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	   IRQVEC INT9,_int9_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	   IRQVEC INT10,_int10_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	   IRQVEC INT11,_int11_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	   IRQVEC INT12,_int12_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	   IRQVEC INT13,_int13_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	   IRQVEC INT14,_int14_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	   IRQVEC INT15,_int15_handler