^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Mark Salter (msalter@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SP B15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * void __switch_to(struct thread_info *prev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * struct thread_info *next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * struct task_struct *tsk) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ENTRY(__switch_to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) LDDW .D2T2 *+B4(THREAD_B15_14),B7:B6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) || MV .L2X A4,B5 ; prev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) || MV .L1X B4,A5 ; next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) || MVC .S2 RILC,B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) STW .D2T2 B3,*+B5(THREAD_PC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) || STDW .D1T1 A13:A12,*+A4(THREAD_A13_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) || MVC .S2 ILC,B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) LDW .D2T2 *+B4(THREAD_PC),B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) || LDDW .D1T1 *+A5(THREAD_A13_12),A13:A12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) STDW .D1T1 A11:A10,*+A4(THREAD_A11_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) || STDW .D2T2 B1:B0,*+B5(THREAD_RICL_ICL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef __DSBT__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) || MVKL .S2 current_ksp,B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) STDW .D2T2 B15:B14,*+B5(THREAD_B15_14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) || STDW .D1T1 A15:A14,*+A4(THREAD_A15_14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef __DSBT__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) || MVKH .S2 current_ksp,B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ;; Switch to next SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MV .S2 B7,SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef __DSBT__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) || STW .D2T2 B7,*+B14(current_ksp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) || STW .D2T2 B7,*B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) || MV .L2 B6,B14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) || LDDW .D1T1 *+A5(THREAD_RICL_ICL),A1:A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) STDW .D2T2 B11:B10,*+B5(THREAD_B11_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) || LDDW .D1T1 *+A5(THREAD_A15_14),A15:A14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) STDW .D2T2 B13:B12,*+B5(THREAD_B13_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) || LDDW .D1T1 *+A5(THREAD_A11_10),A11:A10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) B .S2 B3 ; return in next E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) || LDDW .D2T2 *+B4(THREAD_B13_12),B13:B12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) LDDW .D2T2 *+B4(THREAD_B11_10),B11:B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) NOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MV .L2X A0,B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) || MV .S1 A6,A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MVC .S2 B0,ILC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) || MV .L2X A1,B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MVC .S2 B1,RILC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ENDPROC(__switch_to)