Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/initrd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/dscr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <asm/special_insns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static const char *c6x_soc_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct screen_info screen_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) int c6x_num_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) EXPORT_SYMBOL_GPL(c6x_num_cores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) unsigned int c6x_silicon_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) EXPORT_SYMBOL_GPL(c6x_silicon_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * Device status register. This holds information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * about device configuration needed by some drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) unsigned int c6x_devstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) EXPORT_SYMBOL_GPL(c6x_devstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * Some SoCs have fuse registers holding a unique MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * address. This is parsed out of the device tree with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * the resulting MAC being held here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) unsigned char c6x_fuse_mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) unsigned long memory_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) unsigned long memory_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) EXPORT_SYMBOL(memory_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) unsigned long ram_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) unsigned long ram_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Uncached memory for DMA consistent use (memdma=) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static unsigned long dma_start __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static unsigned long dma_size __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct cpuinfo_c6x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	const char *cpu_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	const char *cpu_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	const char *mmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const char *fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	char *cpu_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	unsigned int core_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	char __cpu_rev[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) unsigned int ticks_per_ns_scaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) EXPORT_SYMBOL(ticks_per_ns_scaled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) unsigned int c6x_core_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void __init get_cpuinfo(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	unsigned cpu_id, rev_id, csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct clk *coreclk = clk_get_sys(NULL, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned long core_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u64 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct cpuinfo_c6x *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	p = &per_cpu(cpu_data, smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!IS_ERR(coreclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		c6x_core_freq = clk_get_rate(coreclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		       "Cannot find core clock frequency. Using 700MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		c6x_core_freq = 700000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	core_khz = c6x_core_freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	do_div(tmp, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ticks_per_ns_scaled = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	csr = get_creg(CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	cpu_id = csr >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	rev_id = (csr >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	p->mmu = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	p->fpu = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	p->cpu_voltage = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	switch (cpu_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		p->cpu_name = "C67x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		p->fpu = "yes";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		p->cpu_name = "C62x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		p->cpu_name = "C64x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		p->cpu_name = "C64x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		p->cpu_name = "C64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		p->cpu_voltage = "1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case 21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		p->cpu_name = "C66X";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		p->cpu_voltage = "1.2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		p->cpu_name = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (cpu_id < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		switch (rev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			if (cpu_id > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				p->cpu_rev = "DM640/DM641/DM642/DM643";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				p->cpu_voltage = "1.2 - 1.4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				p->cpu_rev = "C6201";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				p->cpu_voltage = "2.5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		case 0x2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			p->cpu_rev = "C6201B/C6202/C6211";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			p->cpu_voltage = "1.8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		case 0x3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			p->cpu_rev = "C6202B/C6203/C6204/C6205";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			p->cpu_voltage = "1.5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		case 0x201:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			p->cpu_rev = "C6701 revision 0 (early CPU)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			p->cpu_voltage = "1.8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		case 0x202:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			p->cpu_rev = "C6701/C6711/C6712";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			p->cpu_voltage = "1.8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		case 0x801:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			p->cpu_rev = "C64x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			p->cpu_voltage = "1.5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			p->cpu_rev = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		p->cpu_rev = p->__cpu_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	p->core_id = get_coreid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	for_each_of_cpu_node(node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		++c6x_num_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	node = of_find_node_by_name(NULL, "soc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		if (of_property_read_string(node, "model", &c6x_soc_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			c6x_soc_name = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		c6x_soc_name = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	       p->core_id, p->cpu_name, p->cpu_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	       p->cpu_voltage, c6x_core_freq / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * Early parsing of the command line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static u32 mem_size __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* "mem=" parsing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init early_mem(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mem_size = memparse(p, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* don't remove all of memory when handling "mem={invalid}" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (mem_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) early_param("mem", early_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* "memdma=<size>[@<address>]" parsing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int __init early_memdma(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	dma_size = memparse(p, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (*p == '@')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		dma_start = memparse(p, &p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) early_param("memdma", early_memdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int __init c6x_add_memory(phys_addr_t start, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	static int ram_found __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* We only handle one bank (the one with PAGE_OFFSET) for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (ram_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ram_start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ram_end = start + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ram_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * Do early machine setup and device tree parsing. This is called very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * early on the boot process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) notrace void __init machine_init(unsigned long dt_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	void *dtb = __va(dt_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	void *fdt = __dtb_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* interrupts must be masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	set_creg(IER, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * Set the Interrupt Service Table (IST) to the beginning of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 * vector table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	set_ist(_vectors_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * dtb is passed in from bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * fdt is linked in blob.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (dtb && dtb != fdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		fdt = dtb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	/* Do some early initialization based on the flat device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	early_init_dt_scan(fdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	parse_early_param();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __init setup_arch(char **cmdline_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	phys_addr_t start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u64 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	printk(KERN_INFO "Initializing kernel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* Initialize command line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	*cmdline_p = boot_command_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	memory_end = ram_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	memory_end &= ~(PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* add block that this kernel can use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* reserve kernel text/data/bss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	memblock_reserve(PAGE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			 PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (dma_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		/* align to cacheability granularity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		dma_size = CACHE_REGION_END(dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		if (!dma_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			dma_start = memory_end - dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		/* align to cacheability granularity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		dma_start = CACHE_REGION_START(dma_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/* reserve DMA memory taken from kernel memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		if (memblock_is_region_memory(dma_start, dma_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			memblock_reserve(dma_start, dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	memory_start = PAGE_ALIGN((unsigned int) &_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	       memory_start, memory_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	 * Reserve initrd memory if in kernel memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (initrd_start < initrd_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (memblock_is_region_memory(initrd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 					      initrd_end - initrd_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			memblock_reserve(initrd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 					 initrd_end - initrd_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	init_mm.start_code = (unsigned long) &_stext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	init_mm.end_code   = (unsigned long) &_etext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	init_mm.end_data   = memory_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	init_mm.brk        = memory_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	c6x_cache_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/* Set the whole external memory as non-cacheable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	disable_caching(ram_start, ram_end - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	/* Set caching of external RAM used by Linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	for_each_mem_range(i, &start, &end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		enable_caching(CACHE_REGION_START(start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			       CACHE_REGION_START(end - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_BLK_DEV_INITRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	 * Enable caching for initrd which falls outside kernel memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (initrd_start < initrd_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (!memblock_is_region_memory(initrd_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 					       initrd_end - initrd_start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			enable_caching(CACHE_REGION_START(initrd_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				       CACHE_REGION_START(initrd_end - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 * Disable caching for dma coherent memory taken from kernel memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	if (dma_size && memblock_is_region_memory(dma_start, dma_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		disable_caching(dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 				CACHE_REGION_START(dma_start + dma_size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* Initialize the coherent memory allocator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	coherent_mem_init(dma_start, dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	max_low_pfn = PFN_DOWN(memory_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	min_low_pfn = PFN_UP(memory_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	max_pfn = max_low_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	max_mapnr = max_low_pfn - min_low_pfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	/* Get kmalloc into gear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	paging_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	 * Probe for Device State Configuration Registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	 * We have to do this early in case timer needs to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	 * through DSCR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	dscr_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* We do this early for timer and core clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	c64x_setup_clocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	/* Get CPU info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	get_cpuinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	conswitchp = &dummy_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define cpu_to_ptr(n) ((void *)((long)(n)+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ptr_to_cpu(p) ((long)(p) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int show_cpuinfo(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	int n = ptr_to_cpu(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (n == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			   "soc\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 			   "soc revision\t: 0x%x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			   "soc cores\t: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			   c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	seq_printf(m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		   "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		   "processor\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		   "cpu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		   "core revision\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		   "core voltage\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		   "core id\t\t: %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		   "mmu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		   "fpu\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		   "cpu MHz\t\t: %u\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		   "bogomips\t: %lu.%02lu\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		   n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		   p->cpu_name, p->cpu_rev, p->cpu_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		   p->core_id, p->mmu, p->fpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		   (c6x_core_freq + 500000) / 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		   (loops_per_jiffy/(500000/HZ)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		   (loops_per_jiffy/(5000/HZ))%100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	show_cpuinfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static struct cpu cpu_devices[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int __init topology_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	for_each_present_cpu(i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		register_cpu(&cpu_devices[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) subsys_initcall(topology_init);