Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *  Large parts taken directly from powerpc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _ASM_C6X_IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _ASM_C6X_IRQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/radix-tree.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define irq_canonicalize(irq)  (irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * are reserved. The remaining 12 vectors are used to route SoC interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * These interrupt vectors are prioritized with IRQ 4 having the highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * priority and IRQ 15 having the lowest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * The C64x+ megamodule provides a PIC which combines SoC IRQ sources into a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * single core IRQ vector. There are four combined sources, each of which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * feed into one of the 12 general interrupt vectors. The remaining 8 vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * can each route a single SoC interrupt directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NR_PRIORITY_IRQS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Total number of virq in the platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NR_IRQS		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* This number is used when no interrupt has been assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NO_IRQ		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern void __init init_pic_c64xplus(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern void init_IRQ(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) extern unsigned long irq_err_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* _ASM_C6X_IRQ_H */