^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _ASM_C6X_ELF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _ASM_C6X_ELF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ELF register definitions..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) typedef unsigned long elf_greg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) typedef unsigned long elf_fpreg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ELF_NGREG 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ELF_NFPREG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) typedef elf_greg_t elf_gregset_t[ELF_NGREG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * This is used to ensure we don't load something for the wrong architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define elf_check_arch(x) ((x)->e_machine == EM_TI_C6000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define elf_check_fdpic(x) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define elf_check_const_displacement(x) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ELF_FDPIC_PLAT_INIT(_regs, _exec_map, _interp_map, _dynamic_addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) _regs->b4 = (_exec_map); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) _regs->a6 = (_interp_map); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) _regs->b6 = (_dynamic_addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ELF_FDPIC_CORE_EFLAGS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ELF_CORE_COPY_FPREGS(...) 0 /* No FPU regs to copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * These are used to set parameters in the core dumps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef __LITTLE_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ELF_DATA ELFDATA2LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ELF_DATA ELFDATA2MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ELF_CLASS ELFCLASS32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ELF_ARCH EM_TI_C6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Nothing for now. Need to setup DP... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ELF_PLAT_INIT(_r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USE_ELF_CORE_DUMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ELF_EXEC_PAGESIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ELF_CORE_COPY_REGS(_dest, _regs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) memcpy((char *) &_dest, (char *) _regs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) sizeof(struct pt_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* This yields a mask that user programs can use to figure out what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) instruction set this cpu supports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ELF_HWCAP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* This yields a string that ld.so will use to load implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) specific libraries for optimization. This is more specific in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) intent than poking at uname or /proc/cpuinfo. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ELF_PLATFORM (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* C6X specific section types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SHT_C6000_UNWIND 0x70000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SHT_C6000_PREEMPTMAP 0x70000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SHT_C6000_ATTRIBUTES 0x70000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* C6X specific DT_ tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DT_C6000_DSBT_BASE 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DT_C6000_DSBT_SIZE 0x70000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DT_C6000_PREEMPTMAP 0x70000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DT_C6000_DSBT_INDEX 0x70000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* C6X specific relocs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R_C6000_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R_C6000_ABS32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R_C6000_ABS16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R_C6000_ABS8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R_C6000_PCR_S21 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R_C6000_PCR_S12 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R_C6000_PCR_S10 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R_C6000_PCR_S7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R_C6000_ABS_S16 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R_C6000_ABS_L16 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R_C6000_ABS_H16 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R_C6000_SBR_U15_B 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R_C6000_SBR_U15_H 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define R_C6000_SBR_U15_W 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R_C6000_SBR_S16 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R_C6000_SBR_L16_B 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R_C6000_SBR_L16_H 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R_C6000_SBR_L16_W 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R_C6000_SBR_H16_B 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R_C6000_SBR_H16_H 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R_C6000_SBR_H16_W 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R_C6000_SBR_GOT_U15_W 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R_C6000_SBR_GOT_L16_W 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R_C6000_SBR_GOT_H16_W 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define R_C6000_DSBT_INDEX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define R_C6000_PREL31 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define R_C6000_COPY 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define R_C6000_ALIGN 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define R_C6000_FPHEAD 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define R_C6000_NOCMP 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif /*_ASM_C6X_ELF_H */