^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI C64X clock definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010, 2011 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contributed by: Mark Salter <msalter@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copied heavily from arm/mach-davinci/clock.h, so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2006-2007 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2008-2009 Deep Root Systems, LLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _ASM_C6X_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _ASM_C6X_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* PLL/Reset register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLLCTL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLLM 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLLPRE 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLLDIV1 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLLDIV2 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLLDIV3 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLLPOST 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLLCMD 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLLSTAT 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLLALNCTL 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLLDCHANGE 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLLCKEN 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLLCKSTAT 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLLSYSTAT 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLLDIV4 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLLDIV5 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLLDIV6 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLLDIV7 0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLLDIV8 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLLDIV9 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLLDIV10 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLLDIV11 0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLLDIV12 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PLLDIV13 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PLLDIV14 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PLLDIV15 0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PLLDIV16 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PLLM register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PLLM_PLLM_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PLLM_VAL(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* PREDIV register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLLPREDIV_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLLPREDIV_VAL(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* PLLCTL register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLLCTL_PLLEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PLLCTL_PLLPWRDN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PLLCTL_PLLRST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PLLCTL_PLLDIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PLLCTL_PLLENSRC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PLLCTL_CLKMODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* PLLCMD register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLLCMD_GOSTAT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* PLLSTAT register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PLLSTAT_GOSTAT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* PLLDIV register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLLDIV_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PLLDIV_RATIO_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PLLDIV_RATIO(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct module *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int usecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct list_head children; /* list of children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct list_head childnode; /* parent's child list node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct pll_data *pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long (*recalc) (struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int (*set_rate) (struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int (*round_rate) (struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Clock flags: SoC-specific flags start at BIT(16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ALWAYS_ENABLED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_PLL BIT(2) /* PLL-derived clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PRE_PLL BIT(3) /* source is before PLL mult/div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAX_PLL_SYSCLKS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 input_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 bypass_delay; /* in loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 reset_delay; /* in loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 lock_delay; /* in loops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk sysclks[MAX_PLL_SYSCLKS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* pll_data flag bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PLL_HAS_PRE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PLL_HAS_MUL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PLL_HAS_POST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK(dev, con, ck) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .dev_id = dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .con_id = con, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .clk = ck, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern void c6x_clks_init(struct clk_lookup *clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern int clk_register(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) extern void clk_unregister(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern void c64x_setup_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern struct pll_data c6x_soc_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern struct clk clkin1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern struct clk c6x_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern struct clk c6x_i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern struct clk c6x_watchdog_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern struct clk c6x_mcbsp1_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern struct clk c6x_mcbsp2_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern struct clk c6x_mdio_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif /* _ASM_C6X_CLOCK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags