Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ASM_C6X_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ASM_C6X_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * physically-indexed cache management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define flush_icache_range(s, e)				  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) do {								  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		L1D_cache_block_writeback((s), (e));		  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		L1P_cache_block_invalidate((s), (e));		  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define flush_icache_page(vma, page)					  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) do {								  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	if ((vma)->vm_flags & PROT_EXEC)				  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		L1D_cache_block_writeback_invalidate(page_address(page),  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			(unsigned long) page_address(page) + PAGE_SIZE)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		L1P_cache_block_invalidate(page_address(page),		  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			(unsigned long) page_address(page) + PAGE_SIZE)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) do {						     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	memcpy(dst, src, len);			     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm-generic/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* _ASM_C6X_CACHEFLUSH_H */