Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Port on Texas Instruments TMS320C6x architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _ASM_C6X_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _ASM_C6X_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Cache line size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L1D_CACHE_SHIFT   6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define L1P_CACHE_SHIFT   5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define L2_CACHE_SHIFT    7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * L2 used as cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define L2MODE_SIZE	  L2MODE_256K_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * the L2 line size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define L1_CACHE_SHIFT        L2_CACHE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define L2_CACHE_ALIGN_LOW(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	(((x) & ~(L2_CACHE_BYTES - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define L2_CACHE_ALIGN_UP(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	(((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define L2_CACHE_ALIGN_CNT(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	(((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ARCH_SLAB_MINALIGN	L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  * This is the granularity of hardware cacheability control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CACHEABILITY_ALIGN	0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * Align a physical address to MAR regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CACHE_REGION_START(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	(((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CACHE_REGION_END(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	(((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern void __init c6x_cache_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern void enable_caching(unsigned long start, unsigned long end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern void disable_caching(unsigned long start, unsigned long end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern void L1_cache_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern void L1_cache_on(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void L1P_cache_global_invalidate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern void L1D_cache_global_invalidate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern void L1D_cache_global_writeback(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern void L1D_cache_global_writeback_invalidate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern void L2_cache_set_mode(unsigned int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern void L2_cache_global_writeback_invalidate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern void L2_cache_global_writeback(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) extern void L1D_cache_block_writeback_invalidate(unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 						 unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern void L2_cache_block_writeback_invalidate(unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 						unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern void L2_cache_block_invalidate_nowait(unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 					     unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern void L2_cache_block_writeback_nowait(unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 					    unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 						       unsigned int end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* _ASM_C6X_CACHE_H */