^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) cpu@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) cpu@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) cpu@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) cpu@5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) reg = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cpu@6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) reg = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cpu@7 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) reg = <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) model = "ti,c66x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) model = "tms320c6678";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) core_pic: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) compatible = "ti,c64x+core-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) megamod_pic: interrupt-controller@1800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) compatible = "ti,c64x+megamod-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = <0x1800000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) interrupt-parent = <&core_pic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) cache-controller@1840000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) compatible = "ti,c64x+cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = <0x01840000 0x8400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) timer8: timer@2280000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ti,core-mask = < 0x01 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg = <0x2280000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) timer9: timer@2290000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ti,core-mask = < 0x02 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg = <0x2290000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) timer10: timer@22A0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ti,core-mask = < 0x04 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg = <0x22A0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) timer11: timer@22B0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ti,core-mask = < 0x08 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = <0x22B0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) timer12: timer@22C0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ti,core-mask = < 0x10 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg = <0x22C0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) timer13: timer@22D0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ti,core-mask = < 0x20 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg = <0x22D0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) timer14: timer@22E0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ti,core-mask = < 0x40 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <0x22E0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) timer15: timer@22F0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ti,core-mask = < 0x80 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg = <0x22F0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clock-controller@2310000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) compatible = "ti,c6678-pll", "ti,c64x+pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg = <0x02310000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ti,c64x+pll-bypass-delay = <200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ti,c64x+pll-reset-delay = <12000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ti,c64x+pll-lock-delay = <80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) device-state-controller@2620000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) compatible = "ti,c64x+dscr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg = <0x02620000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ti,dscr-devstat = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ti,dscr-silicon-rev = <0x18 28 0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x114 5 6 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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