^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) cpu@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) cpu@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) cpu@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) cpu@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) cpu@5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) reg = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) model = "tms320c6472";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) core_pic: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) compatible = "ti,c64x+core-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) megamod_pic: interrupt-controller@1800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) compatible = "ti,c64x+megamod-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg = <0x1800000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) interrupt-parent = <&core_pic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) cache-controller@1840000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) compatible = "ti,c64x+cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0x01840000 0x8400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) timer0: timer@25e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ti,core-mask = < 0x01 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0x25e0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) timer1: timer@25f0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ti,core-mask = < 0x02 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x25f0000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) timer2: timer@2600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ti,core-mask = < 0x04 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg = <0x2600000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) timer3: timer@2610000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ti,core-mask = < 0x08 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = <0x2610000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) timer4: timer@2620000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ti,core-mask = < 0x10 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg = <0x2620000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) timer5: timer@2630000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ti,core-mask = < 0x20 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <0x2630000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clock-controller@29a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) compatible = "ti,c6472-pll", "ti,c64x+pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg = <0x029a0000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ti,c64x+pll-bypass-delay = <200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ti,c64x+pll-reset-delay = <12000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ti,c64x+pll-lock-delay = <80000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) device-state-controller@2a80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) compatible = "ti,c64x+dscr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg = <0x02a80000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ti,dscr-devstat = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ti,dscr-silicon-rev = <0x70c 16 0xff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x704 5 6 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ti,dscr-rmii-resets = <0x208 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x20c 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x40c 0x420 0xbea7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x41c 0x420 0xbea7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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