Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		model = "tms320c6457";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		core_pic: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			compatible = "ti,c64x+core-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		megamod_pic: interrupt-controller@1800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			compatible = "ti,c64x+megamod-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			interrupt-parent = <&core_pic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			reg = <0x1800000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		cache-controller@1840000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			compatible = "ti,c64x+cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			reg = <0x01840000 0x8400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		device-state-controller@2880800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			compatible = "ti,c64x+dscr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			reg = <0x02880800 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			ti,dscr-devstat = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			ti,dscr-silicon-rev = <0x18 28 0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 						 0x118 0 0 1 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			ti,dscr-kick-regs = <0x38 0x83E70B13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 					     0x3c 0x95A4F1E0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		timer0: timer@2940000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			reg = <0x2940000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		clock-controller@29a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			compatible = "ti,c6457-pll", "ti,c64x+pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			reg = <0x029a0000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			ti,c64x+pll-bypass-delay = <300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			ti,c64x+pll-reset-delay = <24000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			ti,c64x+pll-lock-delay = <50000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };