^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) device_type = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) model = "ti,c64x+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) model = "tms320c6455";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) core_pic: interrupt-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) compatible = "ti,c64x+core-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Megamodule interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) megamod_pic: interrupt-controller@1800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) compatible = "ti,c64x+megamod-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) reg = <0x1800000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) interrupt-parent = <&core_pic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) cache-controller@1840000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) compatible = "ti,c64x+cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) reg = <0x01840000 0x8400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) emifa@70000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) compatible = "ti,c64x+emifa", "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) reg = <0x70000000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ranges = <0x2 0x0 0xa0000000 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x3 0x0 0xb0000000 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0x4 0x0 0xc0000000 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x5 0x0 0xD0000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ti,dscr-dev-enable = <13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ti,emifa-burst-priority = <255>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ti,emifa-ce-config = <0x00240120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x00240120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x00240122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x00240122>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) timer1: timer@2980000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) compatible = "ti,c64x+timer64";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg = <0x2980000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ti,dscr-dev-enable = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clock-controller@029a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) compatible = "ti,c6455-pll", "ti,c64x+pll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = <0x029a0000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ti,c64x+pll-bypass-delay = <1440>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ti,c64x+pll-reset-delay = <15360>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ti,c64x+pll-lock-delay = <24000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) device-state-config-regs@2a80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) compatible = "ti,c64x+dscr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg = <0x02a80000 0x41000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ti,dscr-devstat = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ti,dscr-silicon-rev = <8 28 0xf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ti,dscr-devstate-ctl-regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) <0 12 0x40008 1 0 0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 12 1 0x40008 3 0 30 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 13 2 0x4002c 1 0xffffffff 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ti,dscr-devstate-stat-regs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <0 10 0x40014 1 0 0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 10 2 0x40018 1 0 0 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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