Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * BPF JIT compiler for ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _BPF_JIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _BPF_JIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/insn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* 5-bit Register Operand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define A64_R(x)	AARCH64_INSN_REG_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define A64_FP		AARCH64_INSN_REG_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define A64_LR		AARCH64_INSN_REG_LR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define A64_ZR		AARCH64_INSN_REG_ZR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define A64_SP		AARCH64_INSN_REG_SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define A64_VARIANT(sf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	((sf) ? AARCH64_INSN_VARIANT_64BIT : AARCH64_INSN_VARIANT_32BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* Compare & branch (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define A64_COMP_BRANCH(sf, Rt, offset, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		AARCH64_INSN_BRANCH_COMP_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Conditional branch (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define A64_COND_BRANCH(cond, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	aarch64_insn_gen_cond_branch_imm(0, offset, cond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define A64_COND_EQ	AARCH64_INSN_COND_EQ /* == */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define A64_COND_NE	AARCH64_INSN_COND_NE /* != */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define A64_COND_CS	AARCH64_INSN_COND_CS /* unsigned >= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define A64_COND_HI	AARCH64_INSN_COND_HI /* unsigned > */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define A64_COND_LS	AARCH64_INSN_COND_LS /* unsigned <= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define A64_COND_CC	AARCH64_INSN_COND_CC /* unsigned < */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define A64_COND_GE	AARCH64_INSN_COND_GE /* signed >= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define A64_COND_GT	AARCH64_INSN_COND_GT /* signed > */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define A64_COND_LE	AARCH64_INSN_COND_LE /* signed <= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define A64_COND_LT	AARCH64_INSN_COND_LT /* signed < */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define A64_B_(cond, imm19) A64_COND_BRANCH(cond, (imm19) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* Unconditional branch (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define A64_BRANCH(offset, type) aarch64_insn_gen_branch_imm(0, offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	AARCH64_INSN_BRANCH_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define A64_B(imm26)  A64_BRANCH((imm26) << 2, NOLINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define A64_BL(imm26) A64_BRANCH((imm26) << 2, LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Unconditional branch (register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define A64_BR(Rn)  aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_NOLINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define A64_BLR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define A64_RET(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Load/store register (register offset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define A64_LS_REG(Rt, Rn, Rm, size, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		AARCH64_INSN_SIZE_##size, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		AARCH64_INSN_LDST_##type##_REG_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define A64_STRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, STORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define A64_LDRB(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 8, LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define A64_STRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, STORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define A64_LDRH(Wt, Xn, Xm)  A64_LS_REG(Wt, Xn, Xm, 16, LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* Load/store register pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		AARCH64_INSN_VARIANT_64BIT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		AARCH64_INSN_LDST_##ls##_PAIR_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define A64_POP(Rt, Rt2, Rn)  A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* Load/store exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define A64_SIZE(sf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	((sf) ? AARCH64_INSN_SIZE_64 : AARCH64_INSN_SIZE_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define A64_LSX(sf, Rt, Rn, Rs, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				       AARCH64_INSN_LDST_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Rt = [Rn]; (atomic) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define A64_LDXR(sf, Rt, Rn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* [Rn] = Rt; (atomic) Rs = [state] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define A64_STXR(sf, Rt, Rn, Rs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* LSE atomics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define A64_STADD(sf, Rn, Rs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	aarch64_insn_gen_stadd(Rn, Rs, A64_SIZE(sf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Add/subtract (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Rd = Rn OP imm12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define A64_ADDS_I(sf, Rd, Rn, imm12) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define A64_SUBS_I(sf, Rd, Rn, imm12) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Rn + imm12; set condition flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define A64_CMN_I(sf, Rn, imm12) A64_ADDS_I(sf, A64_ZR, Rn, imm12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Rn - imm12; set condition flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define A64_CMP_I(sf, Rn, imm12) A64_SUBS_I(sf, A64_ZR, Rn, imm12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Rd = Rn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Bitfield move */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		A64_VARIANT(sf), AARCH64_INSN_BITFIELD_MOVE_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Signed, with sign replication to left and zeros to right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Unsigned, with zeros to left and right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Rd = Rn << shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define A64_LSL(sf, Rd, Rn, shift) ({	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int sz = (sf) ? 64 : 32;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Rd = Rn >> shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Rd = Rn >> shift; signed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Zero extend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Move wide (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define A64_MOVEW(sf, Rd, imm16, shift, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	aarch64_insn_gen_movewide(Rd, imm16, shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		A64_VARIANT(sf), AARCH64_INSN_MOVEWIDE_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Rd = Zeros (for MOVZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * Rd |= imm16 << shift (where shift is {0, 16, 32, 48});
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * Rd = ~Rd; (for MOVN); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Add/subtract (shifted register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Rd = Rn OP Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define A64_ADD(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define A64_SUB(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Rd = -Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Rn - Rm; set condition flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Data-processing (1 source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	A64_VARIANT(sf), AARCH64_INSN_DATA1_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Rd = BSWAPx(Rn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define A64_REV64(Rd, Rn)     A64_DATA1(1, Rd, Rn, REVERSE_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Data-processing (2 source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Rd = Rn OP Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	A64_VARIANT(sf), AARCH64_INSN_DATA2_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Data-processing (3 source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Rd = Ra + Rn * Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Rd = Ra - Rn * Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	A64_VARIANT(sf), AARCH64_INSN_DATA3_MSUB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Rd = Rn * Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Logical (shifted register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Rd = Rn OP Rm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define A64_AND(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define A64_ORR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define A64_EOR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Rn & Rm; set condition flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Logical (immediate) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define A64_LOGIC_IMM(sf, Rd, Rn, imm, type) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u64 imm64 = (sf) ? (u64)imm : (u64)(u32)imm; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_##type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		A64_VARIANT(sf), Rn, Rd, imm64); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Rd = Rn OP imm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define A64_AND_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define A64_ORR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, ORR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define A64_EOR_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, EOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define A64_ANDS_I(sf, Rd, Rn, imm) A64_LOGIC_IMM(sf, Rd, Rn, imm, AND_SETFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Rn & imm; set condition flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define A64_TST_I(sf, Rn, imm) A64_ANDS_I(sf, A64_ZR, Rn, imm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* HINTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define A64_HINT(x) aarch64_insn_gen_hint(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* BTI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define A64_BTI_C  A64_HINT(AARCH64_INSN_HINT_BTIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define A64_BTI_J  A64_HINT(AARCH64_INSN_HINT_BTIJ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define A64_BTI_JC A64_HINT(AARCH64_INSN_HINT_BTIJC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif /* _BPF_JIT_H */