Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Based on arch/arm/mm/flush.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 1995-2002 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) void sync_icache_aliases(void *kaddr, unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	unsigned long addr = (unsigned long)kaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	if (icache_is_aliasing()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		__clean_dcache_area_pou(kaddr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		__flush_icache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		 * Don't issue kick_all_cpus_sync() after I-cache invalidation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		 * for user mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		__flush_icache_range(addr, addr + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 				unsigned long uaddr, void *kaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (vma->vm_flags & VM_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		sync_icache_aliases(kaddr, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * Copy user data from/to a page which is mapped into a different processes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * address space.  Really, we want to allow our "user space" model to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		       unsigned long uaddr, void *dst, const void *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		       unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	memcpy(dst, src, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	flush_ptrace_access(vma, page, uaddr, dst, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __sync_icache_dcache(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	struct page *page = pte_page(pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	if (!test_bit(PG_dcache_clean, &page->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		sync_icache_aliases(page_address(page), page_size(page));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		set_bit(PG_dcache_clean, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXPORT_SYMBOL_GPL(__sync_icache_dcache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  * This function is called when a page has been modified by the kernel. Mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)  * it as dirty for later flushing when mapped in user space (if executable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)  * see __sync_icache_dcache).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void flush_dcache_page(struct page *page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	if (test_bit(PG_dcache_clean, &page->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		clear_bit(PG_dcache_clean, &page->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) EXPORT_SYMBOL(flush_dcache_page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)  * Additional functions defined in assembly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) EXPORT_SYMBOL(__flush_icache_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_ARCH_HAS_PMEM_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void arch_wb_cache_pmem(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	/* Ensure order against any prior non-cacheable writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	dmb(osh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	__clean_dcache_area_pop(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void arch_invalidate_pmem(void *addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 	__inval_dcache_area(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif