^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cache maintenance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/alternative.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/asm-uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * flush_icache_range(start,end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Ensure that the I and D caches are coherent within specified region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * This is typically used when code has been written to a memory region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * and will be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - start - virtual start address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * - end - virtual end address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SYM_FUNC_START(__flush_icache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * __flush_cache_user_range(start,end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Ensure that the I and D caches are coherent within specified region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * This is typically used when code has been written to a memory region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * and will be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * - start - virtual start address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - end - virtual end address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SYM_FUNC_START(__flush_cache_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) uaccess_ttbr0_enable x2, x3, x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) alternative_if ARM64_HAS_CACHE_IDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dsb ishst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) b 7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dcache_line_size x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sub x3, x2, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bic x4, x0, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) add x4, x4, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cmp x4, x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) b.lo 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dsb ish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) alternative_if ARM64_HAS_CACHE_DIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) b 8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) invalidate_icache_by_line x0, x1, x2, x3, 9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 8: mov x0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) uaccess_ttbr0_disable x1, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mov x0, #-EFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) b 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SYM_FUNC_END(__flush_icache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SYM_FUNC_END(__flush_cache_user_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * invalidate_icache_range(start,end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Ensure that the I cache is invalid within specified region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * - start - virtual start address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * - end - virtual end address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SYM_FUNC_START(invalidate_icache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) alternative_if ARM64_HAS_CACHE_DIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mov x0, xzr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) uaccess_ttbr0_enable x2, x3, x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) invalidate_icache_by_line x0, x1, x2, x3, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mov x0, xzr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uaccess_ttbr0_disable x1, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mov x0, #-EFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) b 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SYM_FUNC_END(invalidate_icache_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * __flush_dcache_area(kaddr, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * are cleaned and invalidated to the PoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * - kaddr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SYM_FUNC_START_PI(__flush_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dcache_by_line_op civac, sy, x0, x1, x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SYM_FUNC_END_PI(__flush_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * __clean_dcache_area_pou(kaddr, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * are cleaned to the PoU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * - kaddr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SYM_FUNC_START(__clean_dcache_area_pou)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) alternative_if ARM64_HAS_CACHE_IDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dsb ishst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dcache_by_line_op cvau, ish, x0, x1, x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SYM_FUNC_END(__clean_dcache_area_pou)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * __inval_dcache_area(kaddr, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * are invalidated. Any partial lines at the ends of the interval are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * also cleaned to PoC to prevent data loss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * - kaddr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SYM_FUNC_START_LOCAL(__dma_inv_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SYM_FUNC_START_PI(__inval_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * __dma_inv_area(start, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * - start - virtual start address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) add x1, x1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dcache_line_size x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sub x3, x2, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tst x1, x3 // end cache line aligned?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bic x1, x1, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) b.eq 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dc civac, x1 // clean & invalidate D / U line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 1: tst x0, x3 // start cache line aligned?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bic x0, x0, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) b.eq 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dc civac, x0 // clean & invalidate D / U line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) b 3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 2: dc ivac, x0 // invalidate D / U line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 3: add x0, x0, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cmp x0, x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) b.lo 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dsb sy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SYM_FUNC_END_PI(__inval_dcache_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SYM_FUNC_END(__dma_inv_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * __clean_dcache_area_poc(kaddr, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * are cleaned to the PoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * - kaddr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SYM_FUNC_START_LOCAL(__dma_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SYM_FUNC_START_PI(__clean_dcache_area_poc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* FALLTHROUGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * __dma_clean_area(start, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * - start - virtual start address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dcache_by_line_op cvac, sy, x0, x1, x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SYM_FUNC_END_PI(__clean_dcache_area_poc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SYM_FUNC_END(__dma_clean_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * __clean_dcache_area_pop(kaddr, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * are cleaned to the PoP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * - kaddr - kernel address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SYM_FUNC_START_PI(__clean_dcache_area_pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) alternative_if_not ARM64_HAS_DCPOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) b __clean_dcache_area_poc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dcache_by_line_op cvap, sy, x0, x1, x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SYM_FUNC_END_PI(__clean_dcache_area_pop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * __dma_flush_area(start, size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * clean & invalidate D / U line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * - start - virtual start address of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * - size - size in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SYM_FUNC_START_PI(__dma_flush_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dcache_by_line_op civac, sy, x0, x1, x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SYM_FUNC_END_PI(__dma_flush_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * __dma_map_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SYM_FUNC_START_PI(__dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cmp w2, #DMA_FROM_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) b.eq __dma_inv_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) b __dma_clean_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SYM_FUNC_END_PI(__dma_map_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * __dma_unmap_area(start, size, dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * - start - kernel virtual start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * - size - size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * - dir - DMA direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SYM_FUNC_START_PI(__dma_unmap_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cmp w2, #DMA_TO_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) b.ne __dma_inv_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SYM_FUNC_END_PI(__dma_unmap_area)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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