Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015, 2016 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __KVM_ARM_VGIC_NEW_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __KVM_ARM_VGIC_NEW_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/irqchip/arm-gic-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define PRODUCT_ID_KVM		0x4b	/* ASCII code K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define IMPLEMENTER_ARM		0x43b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define VGIC_ADDR_UNDEF		(-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define INTERRUPT_ID_BITS_SPIS	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define INTERRUPT_ID_BITS_ITS	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define VGIC_PRI_BITS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define VGIC_AFFINITY_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define VGIC_AFFINITY_1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define VGIC_AFFINITY_2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define VGIC_AFFINITY_3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VGIC_AFFINITY_LEVEL(reg, level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * The Userspace encodes the affinity differently from the MPIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Below macro converts vgic userspace format to MPIDR reg format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			    VGIC_AFFINITY_LEVEL(val, 1) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			    VGIC_AFFINITY_LEVEL(val, 2) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			    VGIC_AFFINITY_LEVEL(val, 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * As per Documentation/virt/kvm/devices/arm-vgic-v3.rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * below macros are defined for CPUREG encoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				      KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				      KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 				      KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				      KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * As per Documentation/virt/kvm/devices/arm-vgic-its.rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * below macros are defined for ITS table entry encoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define KVM_ITS_CTE_VALID_SHIFT		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define KVM_ITS_CTE_VALID_MASK		BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define KVM_ITS_CTE_RDBASE_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define KVM_ITS_CTE_ICID_MASK		GENMASK_ULL(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define KVM_ITS_ITE_NEXT_SHIFT		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define KVM_ITS_ITE_PINTID_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define KVM_ITS_ITE_PINTID_MASK		GENMASK_ULL(47, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define KVM_ITS_ITE_ICID_MASK		GENMASK_ULL(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define KVM_ITS_DTE_VALID_SHIFT		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define KVM_ITS_DTE_VALID_MASK		BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define KVM_ITS_DTE_NEXT_SHIFT		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define KVM_ITS_DTE_NEXT_MASK		GENMASK_ULL(62, 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define KVM_ITS_DTE_ITTADDR_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define KVM_ITS_DTE_ITTADDR_MASK	GENMASK_ULL(48, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define KVM_ITS_DTE_SIZE_MASK		GENMASK_ULL(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define KVM_ITS_L1E_VALID_MASK		BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* we only support 64 kB translation table page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define KVM_ITS_L1E_ADDR_MASK		GENMASK_ULL(51, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define KVM_VGIC_V3_RDIST_INDEX_MASK	GENMASK_ULL(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define KVM_VGIC_V3_RDIST_FLAGS_MASK	GENMASK_ULL(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define KVM_VGIC_V3_RDIST_FLAGS_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define KVM_VGIC_V3_RDIST_BASE_MASK	GENMASK_ULL(51, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define KVM_VGIC_V3_RDIST_COUNT_MASK	GENMASK_ULL(63, 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define KVM_VGIC_V3_RDIST_COUNT_SHIFT	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #ifdef CONFIG_DEBUG_SPINLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DEBUG_SPINLOCK_BUG_ON(p) BUG_ON(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DEBUG_SPINLOCK_BUG_ON(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Requires the irq_lock to be held by the caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline bool irq_is_pending(struct vgic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (irq->config == VGIC_CONFIG_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return irq->pending_latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return irq->pending_latch || irq->line_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* Account for the active state as an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (vgic_irq_is_sgi(irq->intid) && irq->source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return hweight8(irq->source) + irq->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return irq_is_pending(irq) || irq->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return vgic_irq_get_lr_count(irq) > 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * This struct provides an intermediate representation of the fields contained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * state to userspace can generate either GICv2 or GICv3 CPU interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * registers regardless of the hardware backed GIC used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct vgic_vmcr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32	grpen0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32	grpen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32	ackctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u32	fiqen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32	cbpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u32	eoim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	u32	abpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u32	bpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	u32	pmr;  /* Priority mask field in the GICC_PMR and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		       * ICC_PMR_EL1 priority field format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct vgic_reg_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	gpa_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		       struct vgic_reg_attr *reg_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		       struct vgic_reg_attr *reg_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct vgic_register_region *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		     gpa_t addr, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			      u32 intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __vgic_put_lpi_locked(struct kvm *kvm, struct vgic_irq *irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool vgic_get_phys_line_level(struct vgic_irq *irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			   unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void vgic_kick_vcpus(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		      phys_addr_t addr, phys_addr_t alignment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			 int offset, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			  int offset, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void vgic_v2_enable(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int vgic_v2_probe(const struct gic_kvm_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int vgic_v2_map_resources(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			     enum vgic_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void vgic_v2_init_lrs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void vgic_v2_load(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void vgic_v2_put(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void vgic_v2_save_state(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline void vgic_get_irq_kref(struct vgic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (irq->intid < VGIC_MIN_LPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	kref_get(&irq->refcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void vgic_v3_enable(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int vgic_v3_probe(const struct gic_kvm_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int vgic_v3_map_resources(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int vgic_v3_save_pending_tables(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bool vgic_v3_check_base(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void vgic_v3_load(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void vgic_v3_put(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bool vgic_has_its(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int kvm_vgic_register_its_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void vgic_enable_lpis(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			 int offset, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			 int offset, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			 u64 id, u64 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				u64 *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				    u32 intid, u64 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int kvm_register_vgic_device(unsigned long type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int vgic_lazy_init(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int vgic_init(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void vgic_debug_init(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void vgic_debug_destroy(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool lock_all_vcpus(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void unlock_all_vcpus(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * num_pri_bits are initialized with HW supported values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * We can rely safely on num_pri_bits even if VM has not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * restored ICC_CTLR_EL1 before restoring APnR registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	switch (cpu_if->num_pri_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case 7: return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case 6: return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	default: return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) vgic_v3_redist_region_full(struct vgic_redist_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (!region->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return (region->free_index >= region->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline size_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (!rdreg->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 							   u32 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct vgic_dist *d = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return (base + size > d->vgic_dist_base) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		(base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int vgic_copy_lpi_list(struct kvm *kvm, struct kvm_vcpu *vcpu, u32 **intid_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			 u32 devid, u32 eventid, struct vgic_irq **irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int vgic_its_inject_cached_translation(struct kvm *kvm, struct kvm_msi *msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void vgic_lpi_translation_cache_init(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void vgic_lpi_translation_cache_destroy(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void vgic_its_invalidate_cache(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) bool vgic_supports_direct_msis(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int vgic_v4_init(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void vgic_v4_teardown(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void vgic_v4_configure_vsgis(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif