^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/irqchip/arm-gic-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <kvm/arm_vgic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/kvm_hyp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/kvm_mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/kvm_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "vgic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static bool group0_trap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static bool group1_trap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static bool common_trap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static bool gicv4_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) cpuif->vgic_hcr |= ICH_HCR_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static bool lr_signals_eoi_mi(u64 lr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) !(lr_val & ICH_LR_HW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 model = vcpu->kvm->arch.vgic.vgic_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int lr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) cpuif->vgic_hcr &= ~ICH_HCR_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (lr = 0; lr < cpuif->used_lrs; lr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u64 val = cpuif->vgic_lr[lr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 intid, cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct vgic_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool is_v2_sgi = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cpuid = val & GICH_LR_PHYSID_CPUID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (model == KVM_DEV_TYPE_ARM_VGIC_V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) intid = val & ICH_LR_VIRTUAL_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) intid = val & GICH_LR_VIRTUALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) is_v2_sgi = vgic_irq_is_sgi(intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Notify fds when the guest EOI'ed a level-triggered IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) kvm_notify_acked_irq(vcpu->kvm, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) intid - VGIC_NR_PRIVATE_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!irq) /* An LPI could have been unmapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) raw_spin_lock(&irq->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Always preserve the active bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) irq->active = !!(val & ICH_LR_ACTIVE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (irq->active && is_v2_sgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) irq->active_source = cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Edge is the only case where we preserve the pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (irq->config == VGIC_CONFIG_EDGE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (val & ICH_LR_PENDING_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (is_v2_sgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) irq->source |= (1 << cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Clear soft pending state when level irqs have been acked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) irq->pending_latch = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Level-triggered mapped IRQs are special because we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * observe rising edges as input to the VGIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * If the guest never acked the interrupt we have to sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * the physical line and set the line level, because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * device state could have changed or we simply need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * process the still pending interrupt later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * If this causes us to lower the level, we have to also clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * the physical active state, since we will otherwise never be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * told when the interrupt becomes asserted again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irq->line_level = vgic_get_phys_line_level(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!irq->line_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) vgic_irq_set_phys_active(irq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) raw_spin_unlock(&irq->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cpuif->used_lrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Requires the irq to be locked already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 model = vcpu->kvm->arch.vgic.vgic_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 val = irq->intid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool allow_pending = true, is_v2_sgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) is_v2_sgi = (vgic_irq_is_sgi(irq->intid) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) model == KVM_DEV_TYPE_ARM_VGIC_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (irq->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= ICH_LR_ACTIVE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (is_v2_sgi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (vgic_irq_is_multi_sgi(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) allow_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) val |= ICH_LR_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (irq->hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val |= ICH_LR_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Never set pending+active on a HW interrupt, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * pending state is kept at the physical distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (irq->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) allow_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (irq->config == VGIC_CONFIG_LEVEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val |= ICH_LR_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Software resampling doesn't work very well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * if we allow P+A, so let's not do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (irq->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) allow_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (allow_pending && irq_is_pending(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val |= ICH_LR_PENDING_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (irq->config == VGIC_CONFIG_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irq->pending_latch = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (vgic_irq_is_sgi(irq->intid) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) model == KVM_DEV_TYPE_ARM_VGIC_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 src = ffs(irq->source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) irq->intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq->source &= ~(1 << (src - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (irq->source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val |= ICH_LR_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Level-triggered mapped IRQs are special because we only observe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * rising edges as input to the VGIC. We therefore lower the line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * level here, so that we can take new virtual IRQs. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * vgic_v3_fold_lr_state for more info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) irq->line_level = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (irq->group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val |= ICH_LR_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 model = vcpu->kvm->arch.vgic.vgic_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ICH_VMCR_ACK_CTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ICH_VMCR_FIQ_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * When emulating GICv3 on GICv3 with SRE=1 on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) vmcr = ICH_VMCR_FIQ_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) cpu_if->vgic_vmcr = vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 model = vcpu->kvm->arch.vgic.vgic_model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) vmcr = cpu_if->vgic_vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ICH_VMCR_ACK_CTL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ICH_VMCR_FIQ_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * When emulating GICv3 on GICv3 with SRE=1 on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) vmcrp->fiqen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) vmcrp->ackctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define INITIAL_PENDBASER_VALUE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void vgic_v3_enable(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * By forcing VMCR to zero, the GIC will restore the binary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * points to their reset values. Anything else resets to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) vgic_v3->vgic_vmcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * If we are emulating a GICv3, we do it in an non-GICv2-compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * way, so we force SRE to 1 to demonstrate this to the guest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Also, we don't support any form of IRQ/FIQ bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * This goes with the spec allowing the value to be RAO/WI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ICC_SRE_EL1_DFB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ICC_SRE_EL1_SRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) vgic_v3->vgic_sre = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ICH_VTR_ID_BITS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ICH_VTR_ID_BITS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ICH_VTR_PRI_BITS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ICH_VTR_PRI_BITS_SHIFT) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Get the show on the road... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) vgic_v3->vgic_hcr = ICH_HCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (group0_trap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (group1_trap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (common_trap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) vgic_v3->vgic_hcr |= ICH_HCR_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int byte_offset, bit_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gpa_t pendbase, ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bool status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) vcpu = irq->target_vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) byte_offset = irq->intid / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) bit_nr = irq->intid % BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ptr = pendbase + byte_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) status = val & (1 << bit_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (irq->target_vcpu != vcpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) irq->pending_latch = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* clear consumed data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val &= ~(1 << bit_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * vgic_v3_save_pending_tables - Save the pending tables into guest RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * kvm lock and all vcpu lock must be held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int vgic_v3_save_pending_tables(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct vgic_dist *dist = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct vgic_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) gpa_t last_ptr = ~(gpa_t)0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int byte_offset, bit_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) gpa_t pendbase, ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) bool stored;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) vcpu = irq->target_vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) byte_offset = irq->intid / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bit_nr = irq->intid % BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ptr = pendbase + byte_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ptr != last_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) last_ptr = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) stored = val & (1U << bit_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (stored == irq->pending_latch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (irq->pending_latch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val |= 1 << bit_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) val &= ~(1 << bit_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * vgic_v3_rdist_overlap - check if a region overlaps with any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * existing redistributor region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * @kvm: kvm handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @base: base of the region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @size: size of region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Return: true if there is an overlap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct vgic_dist *d = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct vgic_redist_region *rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) list_for_each_entry(rdreg, &d->rd_regions, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if ((base + size > rdreg->base) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Check for overlapping regions and for regions crossing the end of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * for base addresses which have already been set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bool vgic_v3_check_base(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct vgic_dist *d = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct vgic_redist_region *rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) list_for_each_entry(rdreg, &d->rd_regions, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (rdreg->base + vgic_v3_rd_region_size(kvm, rdreg) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) rdreg->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) KVM_VGIC_V3_DIST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * which has free space to put a new rdist region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * @rd_regions: redistributor region list head
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * A redistributor regions maps n redistributors, n = region size / (2 x 64kB).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Stride between redistributors is 0 and regions are filled in the index order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Return: the redist region handle, if any, that has space to map a new rdist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct vgic_redist_region *rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) list_for_each_entry(rdreg, rd_regions, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!vgic_v3_redist_region_full(rdreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct list_head *rd_regions = &kvm->arch.vgic.rd_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct vgic_redist_region *rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) list_for_each_entry(rdreg, rd_regions, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (rdreg->index == index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int vgic_v3_map_resources(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct vgic_dist *dist = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) kvm_for_each_vcpu(c, vcpu, kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) kvm_debug("vcpu %d redistributor base not set\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) kvm_err("Need to set vgic distributor addresses first\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (!vgic_v3_check_base(kvm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) kvm_err("VGIC redist and dist frames overlap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * For a VGICv3 we require the userland to explicitly initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * the VGIC before we need to use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!vgic_initialized(kvm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) kvm_err("Unable to register VGICv3 dist MMIO regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (kvm_vgic_global_state.has_gicv4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) vgic_v4_configure_vsgis(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int __init early_group0_trap_cfg(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return strtobool(buf, &group0_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int __init early_group1_trap_cfg(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return strtobool(buf, &group1_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int __init early_common_trap_cfg(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return strtobool(buf, &common_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int __init early_gicv4_enable(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return strtobool(buf, &gicv4_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * @info: pointer to the GIC description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Returns 0 if the VGICv3 has been probed successfully, returns an error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int vgic_v3_probe(const struct gic_kvm_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u64 ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bool has_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) has_v2 = ich_vtr_el2 >> 63;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ich_vtr_el2 = (u32)ich_vtr_el2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * The ListRegs field is 5 bits, but there is an architectural
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * maximum of 16 list registers. Just ignore bit 4...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) kvm_vgic_global_state.can_emulate_gicv2 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* GICv4 support? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (info->has_v4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) kvm_vgic_global_state.has_gicv4 = gicv4_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) kvm_info("GICv4%s support %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) kvm_vgic_global_state.has_gicv4_1 ? ".1" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) gicv4_enable ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) kvm_vgic_global_state.vcpu_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!info->vcpu.start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) kvm_info("GICv3: no GICV resource entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else if (!has_v2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pr_warn(FW_BUG "CPU interface incapable of MMIO access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else if (!PAGE_ALIGNED(info->vcpu.start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pr_warn("GICV physical address 0x%llx not page aligned\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (unsigned long long)info->vcpu.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) kvm_vgic_global_state.vcpu_base = info->vcpu.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) kvm_vgic_global_state.can_emulate_gicv2 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) kvm_err("Cannot register GICv2 KVM device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) kvm_info("vgic-v2@%llx\n", info->vcpu.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kvm_err("Cannot register GICv3 KVM device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (kvm_vgic_global_state.vcpu_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) kvm_info("disabling GICv2 emulation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) group0_trap = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) group1_trap = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (group0_trap || group1_trap || common_trap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) group0_trap ? "G0" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) group1_trap ? "G1" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) common_trap ? "C" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static_branch_enable(&vgic_v3_cpuif_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) kvm_vgic_global_state.vctrl_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) kvm_vgic_global_state.type = VGIC_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void vgic_v3_load(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * VMCR_EL2 save/restore in the world switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (likely(cpu_if->vgic_sre))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) kvm_call_hyp(__vgic_v3_restore_aprs, cpu_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (has_vhe())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __vgic_v3_activate_traps(cpu_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) WARN_ON(vgic_v4_load(vcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (likely(cpu_if->vgic_sre))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cpu_if->vgic_vmcr = kvm_call_hyp_ret(__vgic_v3_read_vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) void vgic_v3_put(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) WARN_ON(vgic_v4_put(vcpu, false));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) vgic_v3_vmcr_sync(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) kvm_call_hyp(__vgic_v3_save_aprs, cpu_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (has_vhe())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __vgic_v3_deactivate_traps(cpu_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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