Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015, 2016 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <kvm/arm_vgic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/kvm_mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "vgic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static inline void vgic_v2_write_lr(int lr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	void __iomem *base = kvm_vgic_global_state.vctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	writel_relaxed(val, base + GICH_LR0 + (lr * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) void vgic_v2_init_lrs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		vgic_v2_write_lr(i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	cpuif->vgic_hcr |= GICH_HCR_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static bool lr_signals_eoi_mi(u32 lr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	       !(lr_val & GICH_LR_HW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * transfer the content of the LRs back into the corresponding ap_list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * - active bit is transferred as is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * - pending bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *   - transferred as is in case of edge sensitive IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *   - set to the line-level (resample time) for level sensitive IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int lr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	DEBUG_SPINLOCK_BUG_ON(!irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	cpuif->vgic_hcr &= ~GICH_HCR_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	for (lr = 0; lr < vgic_cpu->vgic_v2.used_lrs; lr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		u32 val = cpuif->vgic_lr[lr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		u32 cpuid, intid = val & GICH_LR_VIRTUALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		struct vgic_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		/* Extract the source vCPU id from the LR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		cpuid = val & GICH_LR_PHYSID_CPUID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		cpuid &= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		/* Notify fds when the guest EOI'ed a level-triggered SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			kvm_notify_acked_irq(vcpu->kvm, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					     intid - VGIC_NR_PRIVATE_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		raw_spin_lock(&irq->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		/* Always preserve the active bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		irq->active = !!(val & GICH_LR_ACTIVE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (irq->active && vgic_irq_is_sgi(intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			irq->active_source = cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		/* Edge is the only case where we preserve the pending bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (irq->config == VGIC_CONFIG_EDGE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		    (val & GICH_LR_PENDING_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			if (vgic_irq_is_sgi(intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				irq->source |= (1 << cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * Clear soft pending state when level irqs have been acked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			irq->pending_latch = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		 * Level-triggered mapped IRQs are special because we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 * observe rising edges as input to the VGIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		 * If the guest never acked the interrupt we have to sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		 * the physical line and set the line level, because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		 * device state could have changed or we simply need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 * process the still pending interrupt later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		 * If this causes us to lower the level, we have to also clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		 * the physical active state, since we will otherwise never be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		 * told when the interrupt becomes asserted again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			irq->line_level = vgic_get_phys_line_level(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			if (!irq->line_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				vgic_irq_set_phys_active(irq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		raw_spin_unlock(&irq->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	cpuif->used_lrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * Populates the particular LR with the state of a given IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * - for a level sensitive IRQ the pending state value is unchanged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *   it is dictated directly by the input level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * If @irq describes an SGI with multiple sources, we choose the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * lowest-numbered source VCPU and clear that bit in the source bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * The irq_lock must be held by the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 val = irq->intid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	bool allow_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (irq->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		val |= GICH_LR_ACTIVE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (vgic_irq_is_sgi(irq->intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (vgic_irq_is_multi_sgi(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			allow_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			val |= GICH_LR_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (irq->group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		val |= GICH_LR_GROUP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (irq->hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		val |= GICH_LR_HW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		 * Never set pending+active on a HW interrupt, as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		 * pending state is kept at the physical distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		 * level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (irq->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			allow_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		if (irq->config == VGIC_CONFIG_LEVEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			val |= GICH_LR_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			 * Software resampling doesn't work very well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			 * if we allow P+A, so let's not do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			if (irq->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				allow_pending = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (allow_pending && irq_is_pending(irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		val |= GICH_LR_PENDING_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (irq->config == VGIC_CONFIG_EDGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			irq->pending_latch = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (vgic_irq_is_sgi(irq->intid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			u32 src = ffs(irq->source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					   irq->intid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			irq->source &= ~(1 << (src - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			if (irq->source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				val |= GICH_LR_EOI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * Level-triggered mapped IRQs are special because we only observe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * rising edges as input to the VGIC.  We therefore lower the line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * level here, so that we can take new virtual IRQs.  See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * vgic_v2_fold_lr_state for more info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		irq->line_level = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* The GICv2 LR only holds five bits of priority. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		GICH_VMCR_ENABLE_GRP0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		GICH_VMCR_ENABLE_GRP1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		GICH_VMCR_ACK_CTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		GICH_VMCR_FIQ_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		GICH_VMCR_CBPR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		GICH_VMCR_EOI_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		GICH_VMCR_ALIAS_BINPOINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		GICH_VMCR_BINPOINT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	cpu_if->vgic_vmcr = vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u32 vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	vmcr = cpu_if->vgic_vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		GICH_VMCR_ENABLE_GRP0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		GICH_VMCR_ENABLE_GRP1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		GICH_VMCR_ACK_CTL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		GICH_VMCR_FIQ_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		GICH_VMCR_CBPR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		GICH_VMCR_EOI_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			GICH_VMCR_ALIAS_BINPOINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			GICH_VMCR_BINPOINT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) void vgic_v2_enable(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * By forcing VMCR to zero, the GIC will restore the binary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * points to their reset values. Anything else resets to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 * anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Get the show on the road... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* check for overlapping regions and for regions crossing the end of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int vgic_v2_map_resources(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct vgic_dist *dist = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	    IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		kvm_err("Need to set vgic cpu and dist addresses first\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		kvm_err("VGIC CPU and dist frames overlap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 * Initialize the vgic if this hasn't already been done on demand by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 * accessing the vgic state from userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ret = vgic_init(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		kvm_err("Unable to initialize VGIC dynamic data structures\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		kvm_err("Unable to register VGIC MMIO regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 					    kvm_vgic_global_state.vcpu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 					    KVM_VGIC_V2_CPU_SIZE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			kvm_err("Unable to remap VGIC CPU to VCPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)  * vgic_v2_probe - probe for a VGICv2 compatible interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  * @info:	pointer to the GIC description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  * Returns 0 if the VGICv2 has been probed successfully, returns an error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)  * otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int vgic_v2_probe(const struct gic_kvm_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	u32 vtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (!info->vctrl.start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		kvm_err("GICH not present in the firmware table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (!PAGE_ALIGNED(info->vcpu.start) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	    !PAGE_ALIGNED(resource_size(&info->vcpu))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		ret = create_hyp_io_mappings(info->vcpu.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 					     resource_size(&info->vcpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 					     &kvm_vgic_global_state.vcpu_base_va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 					     &kvm_vgic_global_state.vcpu_hyp_va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			kvm_err("Cannot map GICV into hyp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		static_branch_enable(&vgic_v2_cpuif_trap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ret = create_hyp_io_mappings(info->vctrl.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 				     resource_size(&info->vctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 				     &kvm_vgic_global_state.vctrl_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 				     &kvm_vgic_global_state.vctrl_hyp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		kvm_err("Cannot map VCTRL into hyp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		kvm_err("Cannot register GICv2 KVM device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	kvm_vgic_global_state.can_emulate_gicv2 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	kvm_vgic_global_state.vcpu_base = info->vcpu.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	kvm_vgic_global_state.type = VGIC_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (kvm_vgic_global_state.vctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		iounmap(kvm_vgic_global_state.vctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (kvm_vgic_global_state.vcpu_base_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		iounmap(kvm_vgic_global_state.vcpu_base_va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	u64 used_lrs = cpu_if->used_lrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u64 elrsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	elrsr = readl_relaxed(base + GICH_ELRSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (unlikely(used_lrs > 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	for (i = 0; i < used_lrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		if (elrsr & (1UL << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			cpu_if->vgic_lr[i] &= ~GICH_LR_STATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		writel_relaxed(0, base + GICH_LR0 + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void vgic_v2_save_state(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	void __iomem *base = kvm_vgic_global_state.vctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	u64 used_lrs = vcpu->arch.vgic_cpu.vgic_v2.used_lrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (used_lrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		save_lrs(vcpu, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		writel_relaxed(0, base + GICH_HCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) void vgic_v2_restore_state(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	void __iomem *base = kvm_vgic_global_state.vctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	u64 used_lrs = cpu_if->used_lrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (used_lrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		for (i = 0; i < used_lrs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			writel_relaxed(cpu_if->vgic_lr[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 				       base + GICH_LR0 + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) void vgic_v2_load(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	writel_relaxed(cpu_if->vgic_vmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		       kvm_vgic_global_state.vctrl_base + GICH_VMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	writel_relaxed(cpu_if->vgic_apr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		       kvm_vgic_global_state.vctrl_base + GICH_APR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) void vgic_v2_vmcr_sync(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	cpu_if->vgic_vmcr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void vgic_v2_put(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	vgic_v2_vmcr_sync(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	cpu_if->vgic_apr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_APR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }