^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * VGICv3 MMIO handling functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/irqchip/arm-gic-v3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <kvm/iodev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <kvm/arm_vgic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/kvm_emulate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/kvm_arm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/kvm_mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "vgic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "vgic-mmio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* extract @num bytes at @offset bytes offset in data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long extract_bytes(u64 data, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* allows updates of any half of a 64-bit register (or the whole thing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int lower = (offset & 4) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int upper = lower + 8 * len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reg &= ~GENMASK_ULL(upper, lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) val &= GENMASK_ULL(len * 8 - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return reg | ((u64)val << lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool vgic_has_its(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct vgic_dist *dist = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return dist->has_its;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool vgic_supports_direct_msis(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return (kvm_vgic_global_state.has_gicv4_1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The Revision field in the IIDR have the following meanings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Revision 2: Interrupt groups are guest-configurable and signaled using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * their configured groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) switch (addr & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case GICD_CTLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (vgic->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) value |= GICD_CTLR_ENABLE_SS_G1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (vgic->nassgireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) value |= GICD_CTLR_nASSGIreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case GICD_TYPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) value = (value >> 5) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (vgic_has_its(vcpu->kvm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) value |= GICD_TYPER_LPIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case GICD_TYPER2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (kvm_vgic_global_state.has_gicv4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) value = GICD_TYPER2_nASSGIcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case GICD_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) switch (addr & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case GICD_CTLR: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool was_enabled, is_hwsgi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mutex_lock(&vcpu->kvm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) was_enabled = dist->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) is_hwsgi = dist->nassgireq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Not a GICv4.1? No HW SGIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!kvm_vgic_global_state.has_gicv4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val &= ~GICD_CTLR_nASSGIreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Dist stays enabled? nASSGIreq is RO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (was_enabled && dist->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val &= ~GICD_CTLR_nASSGIreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Switching HW SGIs? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dist->nassgireq = val & GICD_CTLR_nASSGIreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (is_hwsgi != dist->nassgireq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) vgic_v4_configure_vsgis(vcpu->kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (kvm_vgic_global_state.has_gicv4_1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) was_enabled != dist->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else if (!was_enabled && dist->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) vgic_kick_vcpus(vcpu->kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mutex_unlock(&vcpu->kvm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case GICD_TYPER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case GICD_TYPER2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case GICD_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* This is at best for documentation purposes... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (addr & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case GICD_TYPER2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case GICD_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case GICD_CTLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Not a GICv4.1? No HW SGIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!kvm_vgic_global_state.has_gicv4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val &= ~GICD_CTLR_nASSGIreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dist->nassgireq = val & GICD_CTLR_nASSGIreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) vgic_mmio_write_v3_misc(vcpu, addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int intid = VGIC_ADDR_TO_INTID(addr, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* The upper word is RAZ for us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!(addr & 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int intid = VGIC_ADDR_TO_INTID(addr, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct vgic_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* The upper word is WI for us since we don't implement Aff3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (addr & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) irq = vgic_get_irq(vcpu->kvm, NULL, intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* We only care about and preserve Aff0, Aff1 and Aff2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irq->mpidr = val & GENMASK(23, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return vgic_cpu->lpis_enabled ? GICR_CTLR_ENABLE_LPIS : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool was_enabled = vgic_cpu->lpis_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!vgic_has_its(vcpu->kvm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (was_enabled && !vgic_cpu->lpis_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) vgic_flush_pending_lpis(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vgic_its_invalidate_cache(vcpu->kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!was_enabled && vgic_cpu->lpis_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) vgic_enable_lpis(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct vgic_redist_region *rdreg = vgic_cpu->rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int target_vcpu_id = vcpu->vcpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gpa_t last_rdist_typer = rdreg->base + GICR_TYPER +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (rdreg->free_index - 1) * KVM_VGIC_V3_REDIST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) value = (u64)(mpidr & GENMASK(23, 0)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) value |= ((target_vcpu_id & 0xffff) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (addr == last_rdist_typer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) value |= GICR_TYPER_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (vgic_has_its(vcpu->kvm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) value |= GICR_TYPER_PLPIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return extract_bytes(value, addr & 7, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static unsigned long vgic_uaccess_read_v3r_typer(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int target_vcpu_id = vcpu->vcpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) value = (u64)(mpidr & GENMASK(23, 0)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) value |= ((target_vcpu_id & 0xffff) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (vgic_has_its(vcpu->kvm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) value |= GICR_TYPER_PLPIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* reporting of the Last bit is not supported for userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return extract_bytes(value, addr & 7, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) switch (addr & 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case GICD_PIDR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* report a GICv3 compliant implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0x3b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static unsigned long vgic_v3_uaccess_read_pending(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * pending state of interrupt is latched in pending_latch variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Userspace will save and restore pending state and line_level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Refer to Documentation/virt/kvm/devices/arm-vgic-v3.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * for handling of ISPENDR and ICPENDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) for (i = 0; i < len * 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bool state = irq->pending_latch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err = irq_get_irqchip_state(irq->host_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) IRQCHIP_STATE_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) WARN_ON(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) value |= (1U << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) for (i = 0; i < len * 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (test_bit(i, &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * pending_latch is set irrespective of irq type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * (level or edge) to avoid dependency that VM should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * restore irq config before pending info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) irq->pending_latch = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* We want to avoid outer shareable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 vgic_sanitise_shareability(u64 field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case GIC_BASER_OuterShareable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return GIC_BASER_InnerShareable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Avoid any inner non-cacheable mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u64 vgic_sanitise_inner_cacheability(u64 field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) switch (field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case GIC_BASER_CACHE_nCnB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case GIC_BASER_CACHE_nC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return GIC_BASER_CACHE_RaWb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Non-cacheable or same-as-inner are OK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u64 vgic_sanitise_outer_cacheability(u64 field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) switch (field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case GIC_BASER_CACHE_SameAsInner:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case GIC_BASER_CACHE_nC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return GIC_BASER_CACHE_SameAsInner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u64 (*sanitise_fn)(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u64 field = (reg & field_mask) >> field_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) field = sanitise_fn(field) << field_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return (reg & ~field_mask) | field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PROPBASER_RES0_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define PENDBASER_RES0_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static u64 vgic_sanitise_pendbaser(u64 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GICR_PENDBASER_SHAREABILITY_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) vgic_sanitise_shareability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) vgic_sanitise_inner_cacheability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) vgic_sanitise_outer_cacheability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) reg &= ~PENDBASER_RES0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static u64 vgic_sanitise_propbaser(u64 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) GICR_PROPBASER_SHAREABILITY_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) vgic_sanitise_shareability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) vgic_sanitise_inner_cacheability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) vgic_sanitise_outer_cacheability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg &= ~PROPBASER_RES0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return extract_bytes(dist->propbaser, addr & 7, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u64 old_propbaser, propbaser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Storing a value with LPIs already enabled is undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (vgic_cpu->lpis_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) old_propbaser = READ_ONCE(dist->propbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) propbaser = old_propbaser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) propbaser = vgic_sanitise_propbaser(propbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } while (cmpxchg64(&dist->propbaser, old_propbaser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) propbaser) != old_propbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u64 value = vgic_cpu->pendbaser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) value &= ~GICR_PENDBASER_PTZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return extract_bytes(value, addr & 7, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u64 old_pendbaser, pendbaser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Storing a value with LPIs already enabled is undefined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (vgic_cpu->lpis_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) old_pendbaser = READ_ONCE(vgic_cpu->pendbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) pendbaser = old_pendbaser;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pendbaser = vgic_sanitise_pendbaser(pendbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pendbaser) != old_pendbaser);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * redistributors, while SPIs are covered by registers in the distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * block. Trying to set private IRQs in this block gets ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * We take some special care here to fix the calculation of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .reg_offset = off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .bits_per_irq = bpi, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .access_flags = acc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .read = vgic_mmio_read_raz, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .write = vgic_mmio_write_wi, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .bits_per_irq = bpi, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .access_flags = acc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .read = rd, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .write = wr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .uaccess_read = ur, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .uaccess_write = uw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct vgic_register_region vgic_v3_dist_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) NULL, vgic_mmio_uaccess_write_v3_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 16, VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) vgic_mmio_read_enable, vgic_mmio_write_senable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) NULL, vgic_uaccess_write_senable, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) vgic_mmio_read_enable, vgic_mmio_write_cenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) NULL, vgic_uaccess_write_cenable, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) vgic_mmio_read_pending, vgic_mmio_write_spending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) vgic_mmio_read_pending, vgic_mmio_write_cpending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) vgic_mmio_read_active, vgic_mmio_write_sactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) vgic_mmio_read_active, vgic_mmio_write_cactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 1, VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct vgic_register_region vgic_v3_rd_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* RD_base registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) vgic_mmio_read_v3r_typer, vgic_mmio_write_wi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) vgic_uaccess_read_v3r_typer, vgic_mmio_uaccess_write_wi, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* SGI_base registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) vgic_mmio_read_group, vgic_mmio_write_group, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) vgic_mmio_read_enable, vgic_mmio_write_senable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) NULL, vgic_uaccess_write_senable, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) vgic_mmio_read_enable, vgic_mmio_write_cenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) NULL, vgic_uaccess_write_cenable, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vgic_mmio_read_pending, vgic_mmio_write_spending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) vgic_v3_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) vgic_mmio_read_pending, vgic_mmio_write_cpending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) vgic_mmio_read_active, vgic_mmio_write_sactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) vgic_mmio_read_active, vgic_mmio_write_cactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) vgic_mmio_read_config, vgic_mmio_write_config, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev->regions = vgic_v3_dist_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return SZ_64K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * vgic_register_redist_iodev - register a single redist iodev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * @vcpu: The VCPU to which the redistributor belongs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Register a KVM iodev for this VCPU's redistributor using the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * provided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Return 0 on success, -ERRNO otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int vgic_register_redist_iodev(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct kvm *kvm = vcpu->kvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct vgic_dist *vgic = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct vgic_redist_region *rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) gpa_t rd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * We may be creating VCPUs before having set the base address for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * redistributor region, in which case we will come back to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * function for all VCPUs when the base address is set. Just return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * without doing any work for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!rdreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!vgic_v3_check_base(kvm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) vgic_cpu->rdreg = rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) rd_dev->base_addr = rd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) rd_dev->iodev_type = IODEV_REDIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) rd_dev->regions = vgic_v3_rd_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rd_dev->redist_vcpu = vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mutex_lock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 2 * SZ_64K, &rd_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mutex_unlock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) rdreg->free_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int vgic_register_all_redist_iodevs(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int c, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) kvm_for_each_vcpu(c, vcpu, kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = vgic_register_redist_iodev(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* The current c failed, so we start with the previous one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) mutex_lock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) for (c--; c >= 0; c--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) vcpu = kvm_get_vcpu(kvm, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) vgic_unregister_redist_iodev(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mutex_unlock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * vgic_v3_insert_redist_region - Insert a new redistributor region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * Performs various checks before inserting the rdist region in the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * Those tests depend on whether the size of the rdist region is known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * (ie. count != 0). The list is sorted by rdist region index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * @kvm: kvm handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * @index: redist region index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * @base: base of the new rdist region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * @count: number of redistributors the region is made of (0 in the old style
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * single region, whose size is induced from the number of vcpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Return 0 on success, < 0 otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int vgic_v3_insert_redist_region(struct kvm *kvm, uint32_t index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) gpa_t base, uint32_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct vgic_dist *d = &kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct vgic_redist_region *rdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct list_head *rd_regions = &d->rd_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) size_t size = count * KVM_VGIC_V3_REDIST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* single rdist region already set ?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (!count && !list_empty(rd_regions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* cross the end of memory ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (base + size < base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (list_empty(rd_regions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) rdreg = list_last_entry(rd_regions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct vgic_redist_region, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (index != rdreg->index + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Cannot add an explicitly sized regions after legacy region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!rdreg->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * For legacy single-region redistributor regions (!count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * check that the redistributor region does not overlap with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * distributor's address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) vgic_dist_overlap(kvm, base, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* collision with any other rdist region? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (vgic_v3_rdist_overlap(kvm, base, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) rdreg = kzalloc(sizeof(*rdreg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!rdreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rdreg->base = VGIC_ADDR_UNDEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ret = vgic_check_ioaddr(kvm, &rdreg->base, base, SZ_64K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rdreg->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rdreg->count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) rdreg->free_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) rdreg->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) list_add_tail(&rdreg->list, rd_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) kfree(rdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = vgic_v3_insert_redist_region(kvm, index, addr, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Register iodevs for each existing VCPU. Adding more VCPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * afterwards will register the iodevs when needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = vgic_register_all_redist_iodevs(kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) const struct vgic_register_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct vgic_io_device iodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct vgic_reg_attr reg_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) gpa_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = vgic_v3_parse_attr(dev, attr, ®_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) vcpu = reg_attr.vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) addr = reg_attr.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) switch (attr->group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) iodev.regions = vgic_v3_dist_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) iodev.base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) iodev.regions = vgic_v3_rd_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) iodev.base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u64 reg, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) id = (attr->attr & KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return vgic_v3_has_cpu_sysregs_attr(vcpu, 0, id, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* We only support aligned 32-bit accesses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (addr & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (!region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * generation register ICC_SGI1R_EL1) with a given VCPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * return -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned long affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int level0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Split the current VCPU's MPIDR into affinity level 0 and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * rest as this is what we have to compare against.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) affinity = kvm_vcpu_get_mpidr_aff(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) affinity &= ~MPIDR_LEVEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* bail out if the upper three levels don't match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (sgi_aff != affinity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Is this VCPU's bit set in the mask ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!(sgi_cpu_mask & BIT(level0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return level0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * The ICC_SGI* registers encode the affinity differently from the MPIDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * so provide a wrapper to use the existing defines to isolate a certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * affinity level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define SGI_AFFINITY_LEVEL(reg, level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * @vcpu: The VCPU requesting a SGI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * @allow_group1: Does the sysreg access allow generation of G1 SGIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * This will trap in sys_regs.c and call this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * target processors as well as a bitmask of 16 Aff0 CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * check for matching ones. If this bit is set, we signal all, but not the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * calling VCPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct kvm *kvm = vcpu->kvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct kvm_vcpu *c_vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u16 target_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u64 mpidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int sgi, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int vcpu_id = vcpu->vcpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) bool broadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mpidr = SGI_AFFINITY_LEVEL(reg, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * We iterate over all VCPUs to find the MPIDRs matching the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * If we have handled one CPU, we clear its bit to detect early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * if we are already finished. This avoids iterating through all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * VCPUs when most of the times we just signal a single VCPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) kvm_for_each_vcpu(c, c_vcpu, kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct vgic_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Exit early if we have dealt with all requested CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!broadcast && target_cpus == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Don't signal the calling VCPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (broadcast && c == vcpu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!broadcast) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int level0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (level0 == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* remove this matching VCPU from the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) target_cpus &= ~BIT(level0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * An access targeting Group0 SGIs can only generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * those, while an access targeting Group1 SGIs can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * generate interrupts of either group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (!irq->group || allow_group1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (!irq->hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* HW SGI? Ask the GIC to inject it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) err = irq_set_irqchip_state(irq->host_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) IRQCHIP_STATE_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int offset, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct vgic_io_device dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .regions = vgic_v3_dist_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return vgic_uaccess(vcpu, &dev, is_write, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int offset, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct vgic_io_device rd_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .regions = vgic_v3_rd_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 intid, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (intid % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (is_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) vgic_write_irq_line_level_info(vcpu, intid, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) *val = vgic_read_irq_line_level_info(vcpu, intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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