Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * VGICv2 MMIO handling functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/irqchip/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/nospec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <kvm/iodev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <kvm/arm_vgic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "vgic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "vgic-mmio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * The Revision field in the IIDR have the following meanings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Revision 1: Report GICv2 interrupts as group 0 instead of group 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Revision 2: Interrupt groups are guest-configurable and signaled using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * 	       their configured groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 					    gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	switch (addr & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	case GIC_DIST_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		value = vgic->enabled ? GICD_ENABLE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	case GIC_DIST_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		value = (value >> 5) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	case GIC_DIST_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			(vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			(IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				    gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				    unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	bool was_enabled = dist->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	switch (addr & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	case GIC_DIST_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		dist->enabled = val & GICD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		if (!was_enabled && dist->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			vgic_kick_vcpus(vcpu->kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case GIC_DIST_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	case GIC_DIST_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		/* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int vgic_mmio_uaccess_write_v2_misc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					   gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					   unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	switch (addr & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	case GIC_DIST_IIDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		if (val != vgic_mmio_read_v2_misc(vcpu, addr, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		 * If we observe a write to GICD_IIDR we know that userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		 * has been updated and has had a chance to cope with older
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		 * kernels (VGICv2 IIDR.Revision == 0) incorrectly reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		 * interrupts as group 1, and therefore we now allow groups to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		 * be user writable.  Doing this by default would break
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 * migration from old kernels to new kernels with legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		 * userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		vcpu->kvm->arch.vgic.v2_groups_user_writable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	vgic_mmio_write_v2_misc(vcpu, addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int vgic_mmio_uaccess_write_v2_group(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 					    gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 					    unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (vcpu->kvm->arch.vgic.v2_groups_user_writable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		vgic_mmio_write_group(vcpu, addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				 gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				 unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int intid = val & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int targets = (val >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int mode = (val >> 24) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case 0x0:		/* as specified by targets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	case 0x1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		targets = (1U << nr_vcpus) - 1;			/* all, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		targets &= ~(1U << source_vcpu->vcpu_id);	/* but self */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case 0x2:		/* this very vCPU only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		targets = (1U << source_vcpu->vcpu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case 0x3:		/* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		struct vgic_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		if (!(targets & (1U << c)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		irq->source |= 1U << source_vcpu->vcpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		vgic_queue_irq_unlock(source_vcpu->kvm, irq, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		vgic_put_irq(source_vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					   gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u64 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		val |= (u64)irq->targets << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				   gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				   unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u8 cpu_mask = GENMASK(atomic_read(&vcpu->kvm->online_vcpus) - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* GICD_ITARGETSR[0-7] are read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (intid < VGIC_NR_PRIVATE_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		int target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		irq->targets = (val >> (i * 8)) & cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		target = irq->targets ? __ffs(irq->targets) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 					    gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u32 intid = addr & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u64 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		val |= (u64)irq->source << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				     gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 				     unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32 intid = addr & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		irq->source &= ~((val >> (i * 8)) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (!irq->source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			irq->pending_latch = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				     gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				     unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	u32 intid = addr & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		raw_spin_lock_irqsave(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		irq->source |= (val >> (i * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (irq->source) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			irq->pending_latch = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		vgic_put_irq(vcpu->kvm, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define GICC_ARCH_VERSION_V2	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* These are for userland accesses only, there is no guest-facing emulation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 					   gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct vgic_vmcr vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	vgic_get_vmcr(vcpu, &vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	switch (addr & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case GIC_CPU_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	case GIC_CPU_PRIMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		 * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		 * the PMR field as GICH_VMCR.VMPriMask rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		 * GICC_PMR.Priority, so we expose the upper five bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		 * priority mask to userspace using the lower bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		 * unsigned long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			GICV_PMR_PRIORITY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	case GIC_CPU_BINPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		val = vmcr.bpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	case GIC_CPU_ALIAS_BINPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		val = vmcr.abpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	case GIC_CPU_IDENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		val = ((PRODUCT_ID_KVM << 20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		       (GICC_ARCH_VERSION_V2 << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		       IMPLEMENTER_ARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 				   gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				   unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct vgic_vmcr vmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	vgic_get_vmcr(vcpu, &vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	switch (addr & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	case GIC_CPU_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	case GIC_CPU_PRIMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		 * Our KVM_DEV_TYPE_ARM_VGIC_V2 device ABI exports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		 * the PMR field as GICH_VMCR.VMPriMask rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		 * GICC_PMR.Priority, so we expose the upper five bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		 * priority mask to userspace using the lower bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		 * unsigned long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			GICV_PMR_PRIORITY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	case GIC_CPU_BINPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		vmcr.bpr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	case GIC_CPU_ALIAS_BINPOINT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		vmcr.abpr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	vgic_set_vmcr(vcpu, &vmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static unsigned long vgic_mmio_read_apr(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 					gpa_t addr, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	int n; /* which APRn is this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	n = (addr >> 2) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (kvm_vgic_global_state.type == VGIC_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		/* GICv2 hardware systems support max. 32 groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if (n != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		return vcpu->arch.vgic_cpu.vgic_v2.vgic_apr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		if (n > vgic_v3_max_apr_idx(vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		n = array_index_nospec(n, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		/* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return vgicv3->vgic_ap1r[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void vgic_mmio_write_apr(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				gpa_t addr, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 				unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	int n; /* which APRn is this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	n = (addr >> 2) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (kvm_vgic_global_state.type == VGIC_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		/* GICv2 hardware systems support max. 32 groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		if (n != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		vcpu->arch.vgic_cpu.vgic_v2.vgic_apr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		struct vgic_v3_cpu_if *vgicv3 = &vcpu->arch.vgic_cpu.vgic_v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (n > vgic_v3_max_apr_idx(vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		n = array_index_nospec(n, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		/* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		vgicv3->vgic_ap1r[n] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct vgic_register_region vgic_v2_dist_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	REGISTER_DESC_WITH_LENGTH_UACCESS(GIC_DIST_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		NULL, vgic_mmio_uaccess_write_v2_misc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		12, VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		vgic_mmio_read_group, vgic_mmio_write_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		NULL, vgic_mmio_uaccess_write_v2_group, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		vgic_mmio_read_enable, vgic_mmio_write_senable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		NULL, vgic_uaccess_write_senable, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		vgic_mmio_read_enable, vgic_mmio_write_cenable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		NULL, vgic_uaccess_write_cenable, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		vgic_mmio_read_pending, vgic_mmio_write_spending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		NULL, vgic_uaccess_write_spending, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		vgic_mmio_read_pending, vgic_mmio_write_cpending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		NULL, vgic_uaccess_write_cpending, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		vgic_mmio_read_active, vgic_mmio_write_sactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		vgic_mmio_read_active, vgic_mmio_write_cactive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		vgic_mmio_read_target, vgic_mmio_write_target, NULL, NULL, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct vgic_register_region vgic_v2_cpu_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		vgic_mmio_read_apr, vgic_mmio_write_apr, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		VGIC_ACCESS_32bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	dev->regions = vgic_v2_dist_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	return SZ_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	const struct vgic_register_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	struct vgic_io_device iodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	struct vgic_reg_attr reg_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	gpa_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	ret = vgic_v2_parse_attr(dev, attr, &reg_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	vcpu = reg_attr.vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	addr = reg_attr.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	switch (attr->group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		iodev.regions = vgic_v2_dist_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		iodev.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		iodev.base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		iodev.regions = vgic_v2_cpu_registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		iodev.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		iodev.base_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	/* We only support aligned 32-bit accesses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	if (addr & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (!region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 			  int offset, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	struct vgic_io_device dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		.regions = vgic_v2_cpu_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 		.nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		.iodev_type = IODEV_CPUIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 			 int offset, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	struct vgic_io_device dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		.regions = vgic_v2_dist_registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		.nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		.iodev_type = IODEV_DIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	return vgic_uaccess(vcpu, &dev, is_write, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }