Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012,2013 - ARM Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Marc Zyngier <marc.zyngier@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Derived from arch/arm/kvm/reset.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/hw_breakpoint.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <kvm/arm_arch_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/fpsimd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/kvm_arm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/kvm_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/kvm_emulate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/kvm_mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/virt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Maximum phys_shift supported for any VM on this host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static u32 kvm_ipa_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * ARMv8 Reset Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define VCPU_RESET_PSTATE_EL1	(PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 				 PSR_F_BIT | PSR_D_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define VCPU_RESET_PSTATE_SVC	(PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				 PSR_AA32_I_BIT | PSR_AA32_F_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) unsigned int kvm_sve_max_vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) int kvm_arm_init_sve(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (system_supports_sve()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		kvm_sve_max_vl = sve_max_virtualisable_vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		 * The get_sve_reg()/set_sve_reg() ioctl interface will need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		 * to be extended with multiple register slice support in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		 * order to support vector lengths greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		 * SVE_VL_ARCH_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			kvm_sve_max_vl = SVE_VL_ARCH_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		 * Don't even try to make use of vector lengths that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		 * aren't available on all CPUs, for now:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if (kvm_sve_max_vl < sve_max_vl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			pr_warn("KVM: SVE vector length for guests limited to %u bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				kvm_sve_max_vl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (!system_supports_sve())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	vcpu->arch.sve_max_vl = kvm_sve_max_vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * Userspace can still customize the vector lengths by writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * KVM_REG_ARM64_SVE_VLS.  Allocation is deferred until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * kvm_arm_vcpu_finalize(), which freezes the configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Finalize vcpu's maximum SVE vector length, allocating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * vcpu->arch.sve_state as necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	vl = vcpu->arch.sve_max_vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 * Responsibility for these properties is shared between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * kvm_arm_init_arch_resources(), kvm_vcpu_enable_sve() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 * set_sve_vls().  Double-check here just to be sure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		    vl > SVE_VL_ARCH_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	buf = kzalloc(SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	vcpu->arch.sve_state = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	switch (feature) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case KVM_ARM_VCPU_SVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (!vcpu_has_sve(vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (kvm_arm_vcpu_sve_finalized(vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return kvm_vcpu_finalize_sve(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	kfree(vcpu->arch.sve_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (vcpu_has_sve(vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * For now make sure that both address/generic pointer authentication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 * features are requested by the userspace together and the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * supports these capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (!test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	    !test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	    !system_has_full_ptr_auth())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_PTRAUTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct kvm_vcpu *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	bool is32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Check that the vcpus are either all 32bit or all 64bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (vcpu_has_feature(tmp, KVM_ARM_VCPU_EL1_32BIT) != is32bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * kvm_reset_vcpu - sets core registers and sys_regs to reset value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * @vcpu: The VCPU pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * This function finds the right table above and sets the registers on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * the virtual CPU struct to their architecturally defined reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * values, except for registers whose reset is deferred until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * kvm_arm_vcpu_finalize().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * ioctl or as part of handling a request issued by another VCPU in the PSCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * handling code.  In the first case, the VCPU will not be loaded, and in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * second case the VCPU will be loaded.  Because this function operates purely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * on the memory-backed values of system registers, we want to do a full put if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * we were loaded (handling a request) and load the values back at the end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * the function.  Otherwise we leave the state alone.  In both cases, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * disable preemption around the vcpu reset as we would otherwise race with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * preempt notifiers which also call put/load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct vcpu_reset_state reset_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	bool loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32 pstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	mutex_lock(&vcpu->kvm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	reset_state = vcpu->arch.reset_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	WRITE_ONCE(vcpu->arch.reset_state.reset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	mutex_unlock(&vcpu->kvm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* Reset PMU outside of the non-preemptible section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	kvm_pmu_vcpu_reset(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	loaded = (vcpu->cpu != -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		kvm_arch_vcpu_put(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (!kvm_arm_vcpu_sve_finalized(vcpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			ret = kvm_vcpu_enable_sve(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		kvm_vcpu_reset_sve(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	    test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		if (kvm_vcpu_enable_ptrauth(vcpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!vcpu_allowed_register_width(vcpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	switch (vcpu->arch.target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			pstate = VCPU_RESET_PSTATE_SVC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			pstate = VCPU_RESET_PSTATE_EL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Reset core registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	vcpu->arch.ctxt.spsr_abt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	vcpu->arch.ctxt.spsr_und = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	vcpu->arch.ctxt.spsr_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	vcpu->arch.ctxt.spsr_fiq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	vcpu_gp_regs(vcpu)->pstate = pstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* Reset system registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	kvm_reset_sys_regs(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * Additional reset state handling that PSCI may have imposed on us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * Must be done after all the sys_reg reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (reset_state.reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		unsigned long target_pc = reset_state.pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		/* Gracefully handle Thumb2 entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			target_pc &= ~1UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			vcpu_set_thumb(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		/* Propagate caller endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		if (reset_state.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			kvm_vcpu_set_be(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		*vcpu_pc(vcpu) = target_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		vcpu_set_reg(vcpu, 0, reset_state.r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	/* Reset timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ret = kvm_timer_vcpu_reset(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		kvm_arch_vcpu_load(vcpu, smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 get_kvm_ipa_limit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return kvm_ipa_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int kvm_set_ipa_limit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	unsigned int parange, tgran_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	u64 mmfr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	parange = cpuid_feature_extract_unsigned_field(mmfr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				ID_AA64MMFR0_PARANGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 * IPA size beyond 48 bits could not be supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 * on either 4K or 16K page size. Hence let's cap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 * it to 48 bits, in case it's reported as larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	 * on the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (PAGE_SIZE != SZ_64K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		parange = min(parange, (unsigned int)ID_AA64MMFR0_PARANGE_48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	 * Stage-2. If not, things will stop very quickly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	switch (PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	case SZ_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		tgran_2 = ID_AA64MMFR0_TGRAN4_2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	case SZ_16K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		tgran_2 = ID_AA64MMFR0_TGRAN16_2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	case SZ_64K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		tgran_2 = ID_AA64MMFR0_TGRAN64_2_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		 ((kvm_ipa_limit < KVM_PHYS_SHIFT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		  " (Reduced IPA size, limited VM/VMM compatibility)" : ""));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	u64 mmfr0, mmfr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	u32 phys_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (phys_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		if (phys_shift > kvm_ipa_limit ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		    phys_shift < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		phys_shift = KVM_PHYS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		if (phys_shift > kvm_ipa_limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			pr_warn_once("%s using unsupported default IPA limit, upgrade your VMM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 				     current->comm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	kvm->arch.vtcr = kvm_get_vtcr(mmfr0, mmfr1, phys_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }