^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) .macro SMCCC instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) \instr #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ldr x4, [sp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ldr x4, [sp, #8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) cbz x4, 1f /* no quirk structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) b.ne 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 1: ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * unsigned long a3, unsigned long a4, unsigned long a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * struct arm_smccc_quirk *quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SYM_FUNC_START(__arm_smccc_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SMCCC smc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SYM_FUNC_END(__arm_smccc_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) EXPORT_SYMBOL(__arm_smccc_smc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * unsigned long a3, unsigned long a4, unsigned long a5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct arm_smccc_quirk *quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SYM_FUNC_START(__arm_smccc_hvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SMCCC hvc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SYM_FUNC_END(__arm_smccc_hvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) EXPORT_SYMBOL(__arm_smccc_hvc)