^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Implementation of MPIDR_EL1 hash algorithm through shifting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and OR'ing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * @dst: register containing hash result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * @rs0: register containing affinity level 0 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * @rs1: register containing affinity level 1 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @rs2: register containing affinity level 2 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @rs3: register containing affinity level 3 bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @mpidr: register containing MPIDR_EL1 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @mask: register containing MPIDR mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Pseudo C-code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *u32 dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * u32 aff0, aff1, aff2, aff3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * u64 mpidr_masked = mpidr & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * aff0 = mpidr_masked & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * aff1 = mpidr_masked & 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * aff2 = mpidr_masked & 0xff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * aff3 = mpidr_masked & 0xff00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Output register: dst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Note: input and output registers must be disjoint register sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) and \mpidr, \mpidr, \mask // mask out MPIDR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) and \dst, \mpidr, #0xff // mask=aff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) lsr \dst ,\dst, \rs0 // dst=aff0>>rs0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) and \mask, \mpidr, #0xff00 // mask = aff1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) lsr \mask ,\mask, \rs1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) orr \dst, \dst, \mask // dst|=(aff1>>rs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) and \mask, \mpidr, #0xff0000 // mask = aff2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) lsr \mask ,\mask, \rs2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) orr \dst, \dst, \mask // dst|=(aff2>>rs2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) and \mask, \mpidr, #0xff00000000 // mask = aff3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) lsr \mask ,\mask, \rs3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) orr \dst, \dst, \mask // dst|=(aff3>>rs3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Save CPU state in the provided sleep_stack_data area, and publish its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * location for cpu_resume()'s use in sleep_save_stash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * cpu_resume() will restore this saved state, and return. Because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * link-register is saved and restored, it will appear to return from this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * function. So that the caller can tell the suspend/resume paths apart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * __cpu_suspend_enter() will always return a non-zero value, whereas the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * path through cpu_resume() will return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * x0 = struct sleep_stack_data area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SYM_FUNC_START(__cpu_suspend_enter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) stp x29, lr, [x0, #SLEEP_STACK_DATA_CALLEE_REGS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) stp x19, x20, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) stp x21, x22, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) stp x23, x24, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+48]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) stp x25, x26, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+64]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) stp x27, x28, [x0,#SLEEP_STACK_DATA_CALLEE_REGS+80]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* save the sp in cpu_suspend_ctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mov x2, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) str x2, [x0, #SLEEP_STACK_DATA_SYSTEM_REGS + CPU_CTX_SP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* find the mpidr_hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ldr_l x1, sleep_save_stash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mrs x7, mpidr_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) adr_l x9, mpidr_hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ldr x10, [x9, #MPIDR_HASH_MASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Following code relies on the struct mpidr_hash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * members size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ldp w3, w4, [x9, #MPIDR_HASH_SHIFTS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) add x1, x1, x8, lsl #3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) str x0, [x1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) stp x29, lr, [sp, #-16]!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bl cpu_do_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ldp x29, lr, [sp], #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mov x0, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SYM_FUNC_END(__cpu_suspend_enter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .pushsection ".idmap.text", "awx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SYM_CODE_START(cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bl init_kernel_el
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bl switch_to_vhe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bl __cpu_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* enable the MMU early - so we can access sleep_save_stash by va */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) adrp x1, swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bl __enable_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ldr x8, =_cpu_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) br x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SYM_CODE_END(cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .ltorg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SYM_FUNC_START(_cpu_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mrs x1, mpidr_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) adr_l x8, mpidr_hash // x8 = struct mpidr_hash virt address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* retrieve mpidr_hash members to compute the hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ldr x2, [x8, #MPIDR_HASH_MASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ldp w3, w4, [x8, #MPIDR_HASH_SHIFTS]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ldp w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* x7 contains hash index, let's use it to grab context pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ldr_l x0, sleep_save_stash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ldr x0, [x0, x7, lsl #3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) add x29, x0, #SLEEP_STACK_DATA_CALLEE_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) add x0, x0, #SLEEP_STACK_DATA_SYSTEM_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* load sp from context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ldr x2, [x0, #CPU_CTX_SP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mov sp, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * cpu_do_resume expects x0 to contain context address pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bl cpu_do_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #if defined(CONFIG_KASAN) && defined(CONFIG_KASAN_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mov x0, sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bl kasan_unpoison_task_stack_below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ldp x19, x20, [x29, #16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ldp x21, x22, [x29, #32]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ldp x23, x24, [x29, #48]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ldp x25, x26, [x29, #64]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ldp x27, x28, [x29, #80]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ldp x29, lr, [x29]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mov x0, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SYM_FUNC_END(_cpu_resume)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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