Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hypervisor stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:	Marc Zyngier <marc.zyngier@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/el2_setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/kvm_arm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/kvm_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/virt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	.pushsection	.hyp.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	.align 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) SYM_CODE_START(__hyp_stub_vectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	ventry	el2_sync_invalid		// Synchronous EL2t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	ventry	el2_irq_invalid			// IRQ EL2t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	ventry	el2_fiq_invalid			// FIQ EL2t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	ventry	el2_error_invalid		// Error EL2t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	ventry	el2_sync_invalid		// Synchronous EL2h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	ventry	el2_irq_invalid			// IRQ EL2h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	ventry	el2_fiq_invalid			// FIQ EL2h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	ventry	el2_error_invalid		// Error EL2h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	ventry	el1_sync			// Synchronous 64-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ventry	el1_irq_invalid			// IRQ 64-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	ventry	el1_fiq_invalid			// FIQ 64-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	ventry	el1_error_invalid		// Error 64-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	ventry	el1_sync_invalid		// Synchronous 32-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	ventry	el1_irq_invalid			// IRQ 32-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	ventry	el1_fiq_invalid			// FIQ 32-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	ventry	el1_error_invalid		// Error 32-bit EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) SYM_CODE_END(__hyp_stub_vectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.align 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) SYM_CODE_START_LOCAL(el1_sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	cmp	x0, #HVC_SET_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	b.ne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	msr	vbar_el2, x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	b	9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 1:	cmp	x0, #HVC_VHE_RESTART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	b.eq	mutate_to_vhe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 2:	cmp	x0, #HVC_SOFT_RESTART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	b.ne	3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	mov	x0, x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mov	x2, x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	mov	x4, x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	mov	x1, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	br	x4				// no return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 3:	cmp	x0, #HVC_RESET_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	beq	9f				// Nothing to reset!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* Someone called kvm_call_hyp() against the hyp-stub... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	mov_q	x0, HVC_STUB_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 9:	mov	x0, xzr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) SYM_CODE_END(el1_sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) // nVHE? No way! Give me the real thing!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) SYM_CODE_START_LOCAL(mutate_to_vhe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	// Sanity check: MMU *must* be off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	mrs	x1, sctlr_el2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	tbnz	x1, #0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	// Needs to be VHE capable, obviously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mrs	x1, id_aa64mmfr1_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	ubfx	x1, x1, #ID_AA64MMFR1_VHE_SHIFT, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	cbz	x1, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	// Check whether VHE is disabled from the command line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	adr_l	x1, id_aa64mmfr1_override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ldr	x2, [x1, FTR_OVR_VAL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ldr	x1, [x1, FTR_OVR_MASK_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	ubfx	x2, x2, #ID_AA64MMFR1_VHE_SHIFT, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ubfx	x1, x1, #ID_AA64MMFR1_VHE_SHIFT, #4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	cmp	x1, xzr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	and	x2, x2, x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	csinv	x2, x2, xzr, ne
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	cbnz	x2, 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 1:	mov_q	x0, HVC_STUB_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	// Engage the VHE magic!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mov_q	x0, HCR_HOST_VHE_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	msr	hcr_el2, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	// Use the EL1 allocated stack, per-cpu offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	mrs	x0, sp_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mov	sp, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mrs	x0, tpidr_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	msr	tpidr_el2, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	// FP configuration, vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	mrs_s	x0, SYS_CPACR_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	msr	cpacr_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	mrs_s	x0, SYS_VBAR_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	msr	vbar_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	// Use EL2 translations for SPE & TRBE and disable access from EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	mrs	x0, mdcr_el2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	bic	x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bic	x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	msr	mdcr_el2, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	// Transfer the MM state from EL1 to EL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	mrs_s	x0, SYS_TCR_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	msr	tcr_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	mrs_s	x0, SYS_TTBR0_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	msr	ttbr0_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mrs_s	x0, SYS_TTBR1_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	msr	ttbr1_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	mrs_s	x0, SYS_MAIR_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	msr	mair_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	// Hack the exception return to stay at EL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mrs	x0, spsr_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	and	x0, x0, #~PSR_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mov	x1, #PSR_MODE_EL2h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	orr	x0, x0, x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	msr	spsr_el1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	b	enter_vhe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SYM_CODE_END(mutate_to_vhe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	// At the point where we reach enter_vhe(), we run with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	// the MMU off (which is enforced by mutate_to_vhe()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	// We thus need to be in the idmap, or everything will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	// explode when enabling the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.pushsection	.idmap.text, "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SYM_CODE_START_LOCAL(enter_vhe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	// Invalidate TLBs before enabling the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	tlbi	vmalle1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	dsb	nsh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	// Enable the EL2 S1 MMU, as set up from EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mrs_s	x0, SYS_SCTLR_EL12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	set_sctlr_el1	x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	// Disable the EL1 S1 MMU for a good measure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mov_q	x0, INIT_SCTLR_EL1_MMU_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	msr_s	SYS_SCTLR_EL12, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mov	x0, xzr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	eret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SYM_CODE_END(enter_vhe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .macro invalid_vector	label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SYM_CODE_START_LOCAL(\label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	b \label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SYM_CODE_END(\label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	invalid_vector	el2_sync_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	invalid_vector	el2_irq_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	invalid_vector	el2_fiq_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	invalid_vector	el2_error_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	invalid_vector	el1_sync_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	invalid_vector	el1_irq_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	invalid_vector	el1_fiq_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	invalid_vector	el1_error_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.popsection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * __hyp_set_vectors: Call this after boot to set the initial hypervisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * vectors as part of hypervisor installation.  On an SMP system, this should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * be called on each CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * x0 must be the physical address of the new vector table, and must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * 2KB aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * Before calling this, you must check that the stub hypervisor is installed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * everywhere, by waiting for any secondary CPUs to be brought up and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * checking that is_hyp_mode_available() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * something else went wrong... in such cases, trying to install a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * hypervisor is unlikely to work as desired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * When you call into your shiny new hypervisor, sp_el2 will contain junk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * so you will need to set that to something sensible at the new hypervisor's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * initialisation entry point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SYM_FUNC_START(__hyp_set_vectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mov	x1, x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mov	x0, #HVC_SET_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	hvc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SYM_FUNC_END(__hyp_set_vectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SYM_FUNC_START(__hyp_reset_vectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	mov	x0, #HVC_RESET_VECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	hvc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SYM_FUNC_END(__hyp_reset_vectors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * Entry point to switch to VHE if deemed capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SYM_FUNC_START(switch_to_vhe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef CONFIG_ARM64_VHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	// Need to have booted at EL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	adr_l	x1, __boot_cpu_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ldr	w0, [x1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	cmp	w0, #BOOT_CPU_MODE_EL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	b.ne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	// and still be at EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	mrs	x0, CurrentEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	cmp	x0, #CurrentEL_EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	b.ne	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	// Turn the world upside down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	mov	x0, #HVC_VHE_RESTART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	hvc	#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SYM_FUNC_END(switch_to_vhe)