Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * FP/SIMD state saving and restoring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Catalin Marinas <catalin.marinas@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/fpsimdmacros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Save the FP registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * x0 - pointer to struct fpsimd_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) SYM_FUNC_START(fpsimd_save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	fpsimd_save x0, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SYM_FUNC_END(fpsimd_save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * Load the FP registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * x0 - pointer to struct fpsimd_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SYM_FUNC_START(fpsimd_load_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	fpsimd_restore x0, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SYM_FUNC_END(fpsimd_load_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifdef CONFIG_ARM64_SVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SYM_FUNC_START(sve_save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	sve_save 0, x1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SYM_FUNC_END(sve_save_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SYM_FUNC_START(sve_load_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	sve_load 0, x1, x2, 3, x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SYM_FUNC_END(sve_load_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SYM_FUNC_START(sve_get_vl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	_sve_rdvl	0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SYM_FUNC_END(sve_get_vl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  * Load SVE state from FPSIMD state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * x0 = pointer to struct fpsimd_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * x1 = VQ - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  * Each SVE vector will be loaded with the first 128-bits taken from FPSIMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  * and the rest zeroed. All the other SVE registers will be zeroed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SYM_FUNC_START(sve_load_from_fpsimd_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		sve_load_vq	x1, x2, x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		fpsimd_restore	x0, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  _for n, 0, 15, _sve_pfalse	\n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		_sve_wrffr	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SYM_FUNC_END(sve_load_from_fpsimd_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Zero all SVE registers but the first 128-bits of each vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SYM_FUNC_START(sve_flush_live)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	sve_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SYM_FUNC_END(sve_flush_live)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif /* CONFIG_ARM64_SVE */