^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Record and handle CPU attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/arch_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/fpsimd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/personality.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/preempt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned int system_serial_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) EXPORT_SYMBOL(system_serial_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int system_serial_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) EXPORT_SYMBOL(system_serial_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * In case the boot CPU is hotpluggable, we record its initial state and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * current state separately. Certain system registers may contain different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * values depending on configuration at or after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct cpuinfo_arm64 boot_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const char *icache_policy_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [ICACHE_POLICY_VPIPT] = "VPIPT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [ICACHE_POLICY_VIPT] = "VIPT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [ICACHE_POLICY_PIPT] = "PIPT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long __icache_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const char *const hwcap_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [KERNEL_HWCAP_FP] = "fp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [KERNEL_HWCAP_ASIMD] = "asimd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [KERNEL_HWCAP_EVTSTRM] = "evtstrm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [KERNEL_HWCAP_AES] = "aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [KERNEL_HWCAP_PMULL] = "pmull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [KERNEL_HWCAP_SHA1] = "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [KERNEL_HWCAP_SHA2] = "sha2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [KERNEL_HWCAP_CRC32] = "crc32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [KERNEL_HWCAP_ATOMICS] = "atomics",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [KERNEL_HWCAP_FPHP] = "fphp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [KERNEL_HWCAP_ASIMDHP] = "asimdhp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [KERNEL_HWCAP_CPUID] = "cpuid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [KERNEL_HWCAP_JSCVT] = "jscvt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [KERNEL_HWCAP_FCMA] = "fcma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [KERNEL_HWCAP_LRCPC] = "lrcpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [KERNEL_HWCAP_DCPOP] = "dcpop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [KERNEL_HWCAP_SHA3] = "sha3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [KERNEL_HWCAP_SM3] = "sm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [KERNEL_HWCAP_SM4] = "sm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [KERNEL_HWCAP_ASIMDDP] = "asimddp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [KERNEL_HWCAP_SHA512] = "sha512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [KERNEL_HWCAP_SVE] = "sve",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [KERNEL_HWCAP_DIT] = "dit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [KERNEL_HWCAP_USCAT] = "uscat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [KERNEL_HWCAP_ILRCPC] = "ilrcpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [KERNEL_HWCAP_FLAGM] = "flagm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [KERNEL_HWCAP_SSBS] = "ssbs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [KERNEL_HWCAP_SB] = "sb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [KERNEL_HWCAP_PACA] = "paca",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [KERNEL_HWCAP_PACG] = "pacg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [KERNEL_HWCAP_DCPODP] = "dcpodp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [KERNEL_HWCAP_SVE2] = "sve2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [KERNEL_HWCAP_SVEAES] = "sveaes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [KERNEL_HWCAP_SVEPMULL] = "svepmull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [KERNEL_HWCAP_SVEBITPERM] = "svebitperm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [KERNEL_HWCAP_SVESHA3] = "svesha3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [KERNEL_HWCAP_SVESM4] = "svesm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [KERNEL_HWCAP_FLAGM2] = "flagm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [KERNEL_HWCAP_FRINT] = "frint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [KERNEL_HWCAP_SVEI8MM] = "svei8mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [KERNEL_HWCAP_SVEF32MM] = "svef32mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [KERNEL_HWCAP_SVEF64MM] = "svef64mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [KERNEL_HWCAP_SVEBF16] = "svebf16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [KERNEL_HWCAP_I8MM] = "i8mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [KERNEL_HWCAP_BF16] = "bf16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [KERNEL_HWCAP_DGH] = "dgh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [KERNEL_HWCAP_RNG] = "rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [KERNEL_HWCAP_BTI] = "bti",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [KERNEL_HWCAP_MTE] = "mte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [KERNEL_HWCAP_ECV] = "ecv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [KERNEL_HWCAP_AFP] = "afp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [KERNEL_HWCAP_RPRES] = "rpres",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const char *const compat_hwcap_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [COMPAT_KERNEL_HWCAP(SWP)] = "swp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [COMPAT_KERNEL_HWCAP(HALF)] = "half",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [COMPAT_KERNEL_HWCAP(VFP)] = "vfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [COMPAT_KERNEL_HWCAP(NEON)] = "neon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [COMPAT_KERNEL_HWCAP(TLS)] = "tls",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const char *const compat_hwcap2_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [COMPAT_KERNEL_HWCAP2(AES)] = "aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif /* CONFIG_COMPAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int c_show(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool compat = personality(current->personality) == PER_LINUX32 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) is_compat_task();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for_each_online_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 midr = cpuinfo->reg_midr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * glibc reads /proc/cpuinfo to determine the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * online processors, looking for lines beginning with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * "processor". Give glibc what it expects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) seq_printf(m, "processor\t: %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (compat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) loops_per_jiffy / (500000UL/HZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) loops_per_jiffy / (5000UL/HZ) % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Dump out the common processor features in a single line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Userspace should read the hwcaps with getauxval(AT_HWCAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * rather than attempting to parse this, but there's a body of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * software which does already (at least for 32-bit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) seq_puts(m, "Features\t:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (compat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (compat_elf_hwcap & (1 << j)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Warn once if any feature should not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * have been present on arm64 platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (WARN_ON_ONCE(!compat_hwcap_str[j]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) seq_printf(m, " %s", compat_hwcap_str[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (compat_elf_hwcap2 & (1 << j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) seq_printf(m, " %s", compat_hwcap2_str[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif /* CONFIG_COMPAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (cpu_have_feature(j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) seq_printf(m, " %s", hwcap_str[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) seq_puts(m, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) seq_printf(m, "CPU implementer\t: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MIDR_IMPLEMENTOR(midr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) seq_printf(m, "CPU architecture: 8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) seq_printf(m, "Serial\t\t: %08x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) system_serial_high, system_serial_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void *c_start(struct seq_file *m, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return *pos < 1 ? (void *)1 : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void *c_next(struct seq_file *m, void *v, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ++*pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void c_stop(struct seq_file *m, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const struct seq_operations cpuinfo_op = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .start = c_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .next = c_next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .stop = c_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .show = c_show
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct kobj_type cpuregs_kobj_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .sysfs_ops = &kobj_sysfs_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * The ARM ARM uses the phrase "32-bit register" to describe a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * no statement is made as to whether the upper 32 bits will or will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * registers, we expose them both as 64 bit values to cater for possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * future expansion without an ABI break.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CPUREGS_ATTR_RO(_name, _field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static ssize_t _name##_show(struct kobject *kobj, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct kobj_attribute *attr, char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (info->reg_midr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return sprintf(buf, "0x%016x\n", info->reg_##_field); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) CPUREGS_ATTR_RO(midr_el1, midr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CPUREGS_ATTR_RO(revidr_el1, revidr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct attribute *cpuregs_id_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) &cpuregs_attr_midr_el1.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) &cpuregs_attr_revidr_el1.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct attribute_group cpuregs_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .attrs = cpuregs_id_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .name = "identification"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int cpuid_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rc = kobject_add(&info->kobj, &dev->kobj, "regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) kobject_del(&info->kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int cpuid_cpu_offline(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (info->kobj.parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) kobject_del(&info->kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int __init cpuinfo_regs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) kobject_init(&info->kobj, &cpuregs_kobj_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cpuid_cpu_online, cpuid_cpu_offline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pr_err("cpuinfo: failed to register hotplug callbacks.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) device_initcall(cpuinfo_regs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 l1ip = CTR_L1IP(info->reg_ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) switch (l1ip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case ICACHE_POLICY_PIPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case ICACHE_POLICY_VPIPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) set_bit(ICACHEF_VPIPT, &__icache_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case ICACHE_POLICY_RESERVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case ICACHE_POLICY_VIPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Assume aliasing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) set_bit(ICACHEF_ALIASING, &__icache_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) info->reg_cntfrq = arch_timer_get_cntfrq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Use the effective value of the CTR_EL0 than the raw value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * with the CLIDR_EL1 fields to avoid triggering false warnings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * when there is a mismatch across the CPUs. Keep track of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * effective value of the CTR_EL0 in our internal records for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * acurate sanity check and feature enablement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) info->reg_ctr = read_cpuid_effective_cachetype();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) info->reg_dczid = read_cpuid(DCZID_EL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) info->reg_midr = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) info->reg_revidr = read_cpuid(REVIDR_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __cpuinfo_store_cpu_32bit(&info->aarch32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (IS_ENABLED(CONFIG_ARM64_SVE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) id_aa64pfr0_sve(info->reg_id_aa64pfr0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) info->reg_zcr = read_zcr_features();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cpuinfo_detect_icache_policy(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void cpuinfo_store_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __cpuinfo_store_cpu(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) void __init cpuinfo_store_boot_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) __cpuinfo_store_cpu(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) boot_cpu_data = *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) init_cpu_features(&boot_cpu_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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