^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Contains CPU specific errata definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/kvm_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static bool __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const struct arm64_midr_revidr *fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 midr = read_cpuid_id(), revidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) if (!is_midr_in_range(midr, &entry->midr_range))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) revidr = read_cpuid(REVIDR_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static bool __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static bool __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) model = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MIDR_ARCHITECTURE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return model == entry->midr_range.model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u64 ctr_raw, ctr_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * We want to make sure that all the CPUs in the system expose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * a consistent CTR_EL0 to make sure that applications behaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * correctly with migration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 1) It is safe if the system doesn't support IDC, as CPU anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * reports IDC = 0, consistent with the rest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * 2) If the system has IDC, it is still safe as we trap CTR_EL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * So, we need to make sure either the raw CTR_EL0 or the effective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ctr_raw = read_cpuid_cachetype() & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ctr_real = read_cpuid_effective_cachetype() & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return (ctr_real != sys) && (ctr_raw != sys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bool enable_uct_trap = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((read_cpuid_cachetype() & mask) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (arm64_ftr_reg_ctrel0.sys_val & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enable_uct_trap = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* ... or if the system is affected by an erratum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (cap->capability == ARM64_WORKAROUND_1542419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enable_uct_trap = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (enable_uct_trap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_ARM64_ERRATUM_1463225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .matches = is_affected_midr_range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CAP_MIDR_ALL_VERSIONS(model) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .matches = is_affected_midr_range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .midr_range = MIDR_ALL_VERSIONS(model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MIDR_FIXED(rev, revidr_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CAP_MIDR_RANGE_LIST(list) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .matches = is_affected_midr_range_list, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .midr_range_list = list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Errata affecting a range of revisions of given model variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Errata affecting a single variant/revision of a model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ERRATA_MIDR_REV(model, var, rev) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ERRATA_MIDR_RANGE(model, var, rev, var, rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Errata affecting all variants/revisions of a given a model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ERRATA_MIDR_ALL_VERSIONS(model) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CAP_MIDR_ALL_VERSIONS(model)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Errata affecting a list of midr ranges, with same work around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ERRATA_MIDR_RANGE_LIST(midr_list) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CAP_MIDR_RANGE_LIST(midr_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const __maybe_unused struct midr_range tx2_family_cpus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static bool __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!is_affected_midr_range_list(entry, scope) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) !is_hyp_mode_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for_each_possible_cpu(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static bool __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int scope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 midr = read_cpuid_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return is_midr_in_range(midr, &range) && has_dic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .midr_range.model = MIDR_QCOM_KRYO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .matches = is_kryo_midr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef CONFIG_ARM64_ERRATUM_1286807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #ifdef CONFIG_CAVIUM_ERRATUM_27456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct midr_range cavium_erratum_27456_cpus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Cavium ThunderX, T88 pass 1.x - 2.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Cavium ThunderX, T81 pass 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_CAVIUM_ERRATUM_30115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct midr_range cavium_erratum_30115_cpus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Cavium ThunderX, T88 pass 1.x - 2.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Cavium ThunderX, T83 pass 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .midr_range.model = MIDR_QCOM_KRYO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .matches = is_kryo_midr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct midr_range workaround_clean_cache[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #if defined(CONFIG_ARM64_ERRATUM_826319) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) defined(CONFIG_ARM64_ERRATUM_827319) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) defined(CONFIG_ARM64_ERRATUM_824069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef CONFIG_ARM64_ERRATUM_819472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Cortex-A53 r0p[01] : ARM errata 819472 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_ARM64_ERRATUM_1418040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * - 1188873 affects r0p0 to r2p0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * - 1418040 affects r0p0 to r3p1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct midr_range erratum_1418040_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Cortex-A76 r0p0 to r3p1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Neoverse-N1 r0p0 to r3p1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #ifdef CONFIG_ARM64_ERRATUM_845719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct midr_range erratum_845719_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Cortex-A53 r0p[01234] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Brahma-B53 r0p[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Kryo2XX Silver rAp4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_ARM64_ERRATUM_843419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct arm64_cpu_capabilities erratum_843419_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Cortex-A53 r0p[01234] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .matches = is_affected_midr_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MIDR_FIXED(0x4, BIT(8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Brahma-B53 r0p[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .matches = is_affected_midr_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct midr_range erratum_speculative_at_list[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #ifdef CONFIG_ARM64_ERRATUM_1165522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Cortex A76 r0p0 to r2p0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_ARM64_ERRATUM_1319367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifdef CONFIG_ARM64_ERRATUM_1530923
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Cortex A55 r0p0 to r2p0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Kryo4xx Silver (rdpe => r1p0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_ARM64_ERRATUM_1463225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct midr_range erratum_1463225[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Cortex-A76 r0p0 - r3p1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct midr_range tsb_flush_fail_cpus[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifdef CONFIG_ARM64_ERRATUM_2067961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #ifdef CONFIG_ARM64_ERRATUM_2054223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) const struct arm64_cpu_capabilities arm64_errata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .desc = "ARM errata 826319, 827319, 824069, or 819472",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .capability = ARM64_WORKAROUND_CLEAN_CACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .cpu_enable = cpu_enable_cache_maint_trap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifdef CONFIG_ARM64_ERRATUM_832075
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Cortex-A57 r0p0 - r1p2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .desc = "ARM erratum 832075",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifdef CONFIG_ARM64_ERRATUM_834220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Cortex-A57 r0p0 - r1p2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .desc = "ARM erratum 834220",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .capability = ARM64_WORKAROUND_834220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #ifdef CONFIG_ARM64_ERRATUM_843419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .desc = "ARM erratum 843419",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .capability = ARM64_WORKAROUND_843419,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .matches = cpucap_multi_entry_cap_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .match_list = erratum_843419_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #ifdef CONFIG_ARM64_ERRATUM_845719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .desc = "ARM erratum 845719",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .capability = ARM64_WORKAROUND_845719,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #ifdef CONFIG_CAVIUM_ERRATUM_23154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Cavium ThunderX, pass 1.x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .desc = "Cavium erratum 23154",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .capability = ARM64_WORKAROUND_CAVIUM_23154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifdef CONFIG_CAVIUM_ERRATUM_27456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .desc = "Cavium erratum 27456",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .capability = ARM64_WORKAROUND_CAVIUM_27456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_CAVIUM_ERRATUM_30115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .desc = "Cavium erratum 30115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .capability = ARM64_WORKAROUND_CAVIUM_30115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .desc = "Mismatched cache type (CTR_EL0)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .capability = ARM64_MISMATCHED_CACHE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .matches = has_mismatched_cache_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .cpu_enable = cpu_enable_trap_ctr_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .matches = cpucap_multi_entry_cap_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .match_list = qcom_erratum_1003_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .capability = ARM64_WORKAROUND_REPEAT_TLBI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .matches = cpucap_multi_entry_cap_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .match_list = arm64_repeat_tlbi_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #ifdef CONFIG_ARM64_ERRATUM_858921
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Cortex-A73 all versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .desc = "ARM erratum 858921",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .capability = ARM64_WORKAROUND_858921,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .desc = "Spectre-v2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .capability = ARM64_SPECTRE_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .matches = has_spectre_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .cpu_enable = spectre_v2_enable_mitigation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #ifdef CONFIG_RANDOMIZE_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Must come after the Spectre-v2 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .desc = "Spectre-v3a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .capability = ARM64_SPECTRE_V3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .matches = has_spectre_v3a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .cpu_enable = spectre_v3a_enable_mitigation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .desc = "Spectre-v4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .capability = ARM64_SPECTRE_V4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .matches = has_spectre_v4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .cpu_enable = spectre_v4_enable_mitigation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .desc = "Spectre-BHB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .capability = ARM64_SPECTRE_BHB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .matches = is_spectre_bhb_affected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .cpu_enable = spectre_bhb_enable_mitigation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #ifdef CONFIG_ARM64_ERRATUM_1418040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .desc = "ARM erratum 1418040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .capability = ARM64_WORKAROUND_1418040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * We need to allow affected CPUs to come in late, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * also need the non-affected CPUs to be able to come
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * in at any point in time. Wonderful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .desc = "ARM errata 1165522, 1319367, or 1530923",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #ifdef CONFIG_ARM64_ERRATUM_1463225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .desc = "ARM erratum 1463225",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .capability = ARM64_WORKAROUND_1463225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .matches = has_cortex_a76_erratum_1463225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .midr_range_list = erratum_1463225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .matches = needs_tx2_tvm_workaround,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #ifdef CONFIG_ARM64_ERRATUM_1542419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* we depend on the firmware portion for correctness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .desc = "ARM erratum 1542419 (kernel portion)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .capability = ARM64_WORKAROUND_1542419,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .matches = has_neoverse_n1_erratum_1542419,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .cpu_enable = cpu_enable_trap_ctr_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #ifdef CONFIG_ARM64_ERRATUM_1508412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* we depend on the firmware portion for correctness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .desc = "ARM erratum 1508412 (kernel portion)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .capability = ARM64_WORKAROUND_1508412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .desc = "ARM erratum 2067961 or 2054223",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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