Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  ARM64 cacheinfo support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Copyright (C) 2015 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cacheinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLIDR_CTYPE(clidr, level)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int cache_line_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	if (coherency_max_size != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		return coherency_max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	return cache_line_size_of_cpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) EXPORT_SYMBOL_GPL(cache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline enum cache_type get_cache_type(int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u64 clidr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (level > MAX_CACHE_LEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		return CACHE_TYPE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	clidr = read_sysreg(clidr_el1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	return CLIDR_CTYPE(clidr, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void ci_leaf_init(struct cacheinfo *this_leaf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			 enum cache_type type, unsigned int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	this_leaf->level = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	this_leaf->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int init_cache_level(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	unsigned int ctype, level, leaves, fw_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		ctype = get_cache_type(level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		if (ctype == CACHE_TYPE_NOCACHE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			level--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		/* Separate instruction and data caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		fw_level = of_find_last_cache_level(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		fw_level = acpi_find_last_cache_level(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if (level < fw_level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		 * some external caches not specified in CLIDR_EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		 * the information may be available in the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		 * only unified external caches are considered here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		leaves += (fw_level - level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		level = fw_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	this_cpu_ci->num_levels = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	this_cpu_ci->num_leaves = leaves;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int populate_cache_leaves(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	unsigned int level, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 	enum cache_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	struct cacheinfo *this_leaf = this_cpu_ci->info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	     idx < this_cpu_ci->num_leaves; idx++, level++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 		type = get_cache_type(level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 		if (type == CACHE_TYPE_SEPARATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 			ci_leaf_init(this_leaf++, type, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }