Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Based on arch/arm/kernel/asm-offsets.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1995-2003 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *               2001-2002 Keith Owens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/arm_sdei.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/preempt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/signal32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/kbuild.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) int main(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)   DEFINE(TSK_ACTIVE_MM,		offsetof(struct task_struct, active_mm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)   DEFINE(TSK_TI_FLAGS,		offsetof(struct task_struct, thread_info.flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)   DEFINE(TSK_TI_PREEMPT,	offsetof(struct task_struct, thread_info.preempt_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)   DEFINE(TSK_TI_ADDR_LIMIT,	offsetof(struct task_struct, thread_info.addr_limit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifdef CONFIG_ARM64_SW_TTBR0_PAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)   DEFINE(TSK_TI_TTBR0,		offsetof(struct task_struct, thread_info.ttbr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifdef CONFIG_SHADOW_CALL_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)   DEFINE(TSK_TI_SCS_BASE,	offsetof(struct task_struct, thread_info.scs_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)   DEFINE(TSK_TI_SCS_SP,		offsetof(struct task_struct, thread_info.scs_sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)   DEFINE(TSK_STACK,		offsetof(struct task_struct, stack));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #ifdef CONFIG_STACKPROTECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)   DEFINE(TSK_STACK_CANARY,	offsetof(struct task_struct, stack_canary));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)   DEFINE(THREAD_CPU_CONTEXT,	offsetof(struct task_struct, thread.cpu_context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)   DEFINE(THREAD_SCTLR_USER,	offsetof(struct task_struct, thread.sctlr_user));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #ifdef CONFIG_ARM64_PTR_AUTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)   DEFINE(THREAD_KEYS_USER,	offsetof(struct task_struct, thread.keys_user));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)   DEFINE(THREAD_KEYS_KERNEL,	offsetof(struct task_struct, thread.keys_kernel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #ifdef CONFIG_ARM64_MTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)   DEFINE(THREAD_MTE_CTRL,	offsetof(struct task_struct, thread.mte_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)   DEFINE(S_X0,			offsetof(struct pt_regs, regs[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)   DEFINE(S_X2,			offsetof(struct pt_regs, regs[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)   DEFINE(S_X4,			offsetof(struct pt_regs, regs[4]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)   DEFINE(S_X6,			offsetof(struct pt_regs, regs[6]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)   DEFINE(S_X8,			offsetof(struct pt_regs, regs[8]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)   DEFINE(S_X10,			offsetof(struct pt_regs, regs[10]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)   DEFINE(S_X12,			offsetof(struct pt_regs, regs[12]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)   DEFINE(S_X14,			offsetof(struct pt_regs, regs[14]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)   DEFINE(S_X16,			offsetof(struct pt_regs, regs[16]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)   DEFINE(S_X18,			offsetof(struct pt_regs, regs[18]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)   DEFINE(S_X20,			offsetof(struct pt_regs, regs[20]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)   DEFINE(S_X22,			offsetof(struct pt_regs, regs[22]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)   DEFINE(S_X24,			offsetof(struct pt_regs, regs[24]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)   DEFINE(S_X26,			offsetof(struct pt_regs, regs[26]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)   DEFINE(S_X28,			offsetof(struct pt_regs, regs[28]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)   DEFINE(S_FP,			offsetof(struct pt_regs, regs[29]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)   DEFINE(S_LR,			offsetof(struct pt_regs, regs[30]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)   DEFINE(S_SP,			offsetof(struct pt_regs, sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)   DEFINE(S_PSTATE,		offsetof(struct pt_regs, pstate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)   DEFINE(S_PC,			offsetof(struct pt_regs, pc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)   DEFINE(S_SYSCALLNO,		offsetof(struct pt_regs, syscallno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)   DEFINE(S_ORIG_ADDR_LIMIT,	offsetof(struct pt_regs, orig_addr_limit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)   DEFINE(S_PMR_SAVE,		offsetof(struct pt_regs, pmr_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)   DEFINE(S_STACKFRAME,		offsetof(struct pt_regs, stackframe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)   DEFINE(S_FRAME_SIZE,		sizeof(struct pt_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)   DEFINE(COMPAT_SIGFRAME_REGS_OFFSET,		offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)   DEFINE(COMPAT_RT_SIGFRAME_REGS_OFFSET,	offsetof(struct compat_rt_sigframe, sig.uc.uc_mcontext.arm_r0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)   DEFINE(MM_CONTEXT_ID,		offsetof(struct mm_struct, context.id.counter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)   DEFINE(VMA_VM_MM,		offsetof(struct vm_area_struct, vm_mm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)   DEFINE(VMA_VM_FLAGS,		offsetof(struct vm_area_struct, vm_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)   DEFINE(VM_EXEC,	       	VM_EXEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)   DEFINE(PAGE_SZ,	       	PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)   DEFINE(DMA_TO_DEVICE,		DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)   DEFINE(DMA_FROM_DEVICE,	DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)   DEFINE(PREEMPT_DISABLE_OFFSET, PREEMPT_DISABLE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)   DEFINE(SOFTIRQ_SHIFT, SOFTIRQ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)   DEFINE(IRQ_CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)   DEFINE(CPU_BOOT_STACK,	offsetof(struct secondary_data, stack));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)   DEFINE(CPU_BOOT_TASK,		offsetof(struct secondary_data, task));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)   DEFINE(FTR_OVR_VAL_OFFSET,	offsetof(struct arm64_ftr_override, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)   DEFINE(FTR_OVR_MASK_OFFSET,	offsetof(struct arm64_ftr_override, mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_KVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)   DEFINE(VCPU_CONTEXT,		offsetof(struct kvm_vcpu, arch.ctxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)   DEFINE(VCPU_FAULT_DISR,	offsetof(struct kvm_vcpu, arch.fault.disr_el1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)   DEFINE(VCPU_WORKAROUND_FLAGS,	offsetof(struct kvm_vcpu, arch.workaround_flags));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)   DEFINE(VCPU_HCR_EL2,		offsetof(struct kvm_vcpu, arch.hcr_el2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)   DEFINE(CPU_USER_PT_REGS,	offsetof(struct kvm_cpu_context, regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)   DEFINE(CPU_APIAKEYLO_EL1,	offsetof(struct kvm_cpu_context, sys_regs[APIAKEYLO_EL1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)   DEFINE(CPU_APIBKEYLO_EL1,	offsetof(struct kvm_cpu_context, sys_regs[APIBKEYLO_EL1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)   DEFINE(CPU_APDAKEYLO_EL1,	offsetof(struct kvm_cpu_context, sys_regs[APDAKEYLO_EL1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)   DEFINE(CPU_APDBKEYLO_EL1,	offsetof(struct kvm_cpu_context, sys_regs[APDBKEYLO_EL1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)   DEFINE(CPU_APGAKEYLO_EL1,	offsetof(struct kvm_cpu_context, sys_regs[APGAKEYLO_EL1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)   DEFINE(HOST_CONTEXT_VCPU,	offsetof(struct kvm_cpu_context, __hyp_running_vcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)   DEFINE(HOST_DATA_CONTEXT,	offsetof(struct kvm_host_data, host_ctxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)   DEFINE(NVHE_INIT_MAIR_EL2,	offsetof(struct kvm_nvhe_init_params, mair_el2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)   DEFINE(NVHE_INIT_TCR_EL2,	offsetof(struct kvm_nvhe_init_params, tcr_el2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)   DEFINE(NVHE_INIT_TPIDR_EL2,	offsetof(struct kvm_nvhe_init_params, tpidr_el2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)   DEFINE(NVHE_INIT_STACK_HYP_VA,	offsetof(struct kvm_nvhe_init_params, stack_hyp_va));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)   DEFINE(NVHE_INIT_PGD_PA,	offsetof(struct kvm_nvhe_init_params, pgd_pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)   DEFINE(NVHE_INIT_HCR_EL2,	offsetof(struct kvm_nvhe_init_params, hcr_el2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)   DEFINE(NVHE_INIT_VTTBR,	offsetof(struct kvm_nvhe_init_params, vttbr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)   DEFINE(NVHE_INIT_VTCR,	offsetof(struct kvm_nvhe_init_params, vtcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #ifdef CONFIG_CPU_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)   DEFINE(CPU_CTX_SP,		offsetof(struct cpu_suspend_ctx, sp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)   DEFINE(MPIDR_HASH_MASK,	offsetof(struct mpidr_hash, mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)   DEFINE(MPIDR_HASH_SHIFTS,	offsetof(struct mpidr_hash, shift_aff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)   DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS,	offsetof(struct sleep_stack_data, system_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)   DEFINE(SLEEP_STACK_DATA_CALLEE_REGS,	offsetof(struct sleep_stack_data, callee_saved_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)   DEFINE(ARM_SMCCC_RES_X0_OFFS,		offsetof(struct arm_smccc_res, a0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)   DEFINE(ARM_SMCCC_RES_X2_OFFS,		offsetof(struct arm_smccc_res, a2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)   DEFINE(ARM_SMCCC_QUIRK_ID_OFFS,	offsetof(struct arm_smccc_quirk, id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)   DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS,	offsetof(struct arm_smccc_quirk, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)   DEFINE(HIBERN_PBE_ORIG,	offsetof(struct pbe, orig_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)   DEFINE(HIBERN_PBE_ADDR,	offsetof(struct pbe, address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)   DEFINE(HIBERN_PBE_NEXT,	offsetof(struct pbe, next));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)   DEFINE(ARM64_FTR_SYSVAL,	offsetof(struct arm64_ftr_reg, sys_val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)   DEFINE(TRAMP_VALIAS,		TRAMP_VALIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_ARM_SDE_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)   DEFINE(SDEI_EVENT_INTREGS,	offsetof(struct sdei_registered_event, interrupted_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)   DEFINE(SDEI_EVENT_PRIORITY,	offsetof(struct sdei_registered_event, priority));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #ifdef CONFIG_ARM64_PTR_AUTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)   DEFINE(PTRAUTH_USER_KEY_APIA,		offsetof(struct ptrauth_keys_user, apia));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)   DEFINE(PTRAUTH_KERNEL_KEY_APIA,	offsetof(struct ptrauth_keys_kernel, apia));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)   BLANK();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)   return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }