^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Based on arch/arm/include/asm/traps.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __ASM_TRAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __ASM_TRAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/esr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct pt_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct undef_hook {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 instr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 instr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u64 pstate_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u64 pstate_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int (*fn)(struct pt_regs *regs, u32 instr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void register_undef_hook(struct undef_hook *hook);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void unregister_undef_hook(struct undef_hook *hook);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void force_signal_inject(int signal, int code, unsigned long address, unsigned int err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void arm64_notify_segfault(unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Move regs->pc to next instruction and do necessary setup before it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * is executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline int __in_irqentry_text(unsigned long ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return ptr >= (unsigned long)&__irqentry_text_start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ptr < (unsigned long)&__irqentry_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline int in_entry_text(unsigned long ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ptr >= (unsigned long)&__entry_text_start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ptr < (unsigned long)&__entry_text_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * to indicate whether this ESR has a RAS encoding. CPUs without this feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * have a ISS-Valid bit in the same position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * If this bit is set, we know its not a RAS SError.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * errors share the same encoding as an all-zeros encoding from a CPU that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * doesn't support RAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline bool arm64_is_ras_serror(u32 esr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) WARN_ON(preemptible());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (esr & ESR_ELx_IDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Return the AET bits from a RAS SError's ESR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * It is implementation defined whether Uncategorized errors are containable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * We treat them as Uncontainable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Non-RAS SError's are reported as Uncontained/Uncategorized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline u32 arm64_ras_serror_get_severity(u32 esr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 aet = esr & ESR_ELx_AET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!arm64_is_ras_serror(esr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Not a RAS error, we can't interpret the ESR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return ESR_ELx_AET_UC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * AET is RES0 if 'the value returned in the DFSC field is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * [ESR_ELx_FSC_SERROR]'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* No severity information : Uncategorized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ESR_ELx_AET_UC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return aet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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