^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Macros for accessing system registers with older binutils.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Catalin Marinas <catalin.marinas@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_SYSREG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_SYSREG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kasan-tags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ARMv8 ARM reserves the following encoding for system registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * C5.2, version:ARM DDI 0487A.f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * [20-19] : Op0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * [18-16] : Op1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * [15-12] : CRn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * [11-8] : CRm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * [7-5] : Op2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define Op0_shift 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define Op0_mask 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define Op1_shift 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define Op1_mask 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRn_shift 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CRn_mask 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CRm_shift 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CRm_mask 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define Op2_shift 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define Op2_mask 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define sys_reg(op0, op1, crn, crm, op2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ((op2) << Op2_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define sys_insn sys_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #ifndef CONFIG_BROKEN_GAS_INST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) // The space separator is omitted so that __emit_inst(x) can be parsed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) // either an assembler directive or an assembler macro argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define __emit_inst(x) .inst(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #else /* CONFIG_BROKEN_GAS_INST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #ifndef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define __INSTR_BSWAP(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #else /* CONFIG_CPU_BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (((x) << 8) & 0x00ff0000) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (((x) >> 8) & 0x0000ff00) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (((x) >> 24) & 0x000000ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* CONFIG_CPU_BIG_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define __emit_inst(x) .long __INSTR_BSWAP(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #else /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif /* CONFIG_BROKEN_GAS_INST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Instructions for modifying PSTATE fields.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * for accessing PSTATE fields have the following encoding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Op0 = 0, CRn = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * CRm = Imm4 for the instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Rt = 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PSTATE_Imm_shift CRm_shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PSTATE_PAN pstate_field(0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PSTATE_UAO pstate_field(0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PSTATE_SSBS pstate_field(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PSTATE_TCO pstate_field(3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * System registers, organised loosely by encoding but grouped together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SYS_PAR_EL1_F BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SYS_PAR_EL1_FST GENMASK(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*** Statistical Profiling Extension ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* ID registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SYS_PMSIDR_EL1_FE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SYS_PMSIDR_EL1_FT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SYS_PMSIDR_EL1_FL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SYS_PMSIDR_EL1_LDS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SYS_PMSIDR_EL1_ERND_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SYS_PMBIDR_EL1_P_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SYS_PMBIDR_EL1_F_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Sampling controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SYS_PMSCR_EL1_E0SPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SYS_PMSCR_EL1_E1SPE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SYS_PMSCR_EL1_CX_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SYS_PMSCR_EL1_PA_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SYS_PMSCR_EL1_TS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SYS_PMSCR_EL1_PCT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SYS_PMSCR_EL2_E2SPE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SYS_PMSCR_EL2_CX_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SYS_PMSCR_EL2_PA_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SYS_PMSCR_EL2_TS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SYS_PMSCR_EL2_PCT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SYS_PMSIRR_EL1_RND_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Filtering controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SYS_PMSFCR_EL1_FE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SYS_PMSFCR_EL1_FT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SYS_PMSFCR_EL1_FL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SYS_PMSFCR_EL1_B_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SYS_PMSFCR_EL1_LD_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SYS_PMSFCR_EL1_ST_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Buffer controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SYS_PMBLIMITR_EL1_E_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SYS_PMBLIMITR_EL1_FM_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Buffer error reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SYS_PMBSR_EL1_COLL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SYS_PMBSR_EL1_S_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SYS_PMBSR_EL1_EA_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SYS_PMBSR_EL1_DL_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SYS_PMBSR_EL1_EC_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SYS_PMBSR_EL1_EC_MASK 0x3fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*** End of Statistical Profiling Extension ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * TRBE Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TRBLIMITR_LIMIT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TRBLIMITR_NVM BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TRBLIMITR_TRIG_MODE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TRBLIMITR_FILL_MODE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TRBLIMITR_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TRBPTR_PTR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TRBBASER_BASE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define TRBSR_EC_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TRBSR_EC_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TRBSR_IRQ BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TRBSR_TRG BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TRBSR_WRAP BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define TRBSR_ABORT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TRBSR_STOP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define TRBSR_MSS_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TRBSR_MSS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define TRBSR_BSC_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TRBSR_BSC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define TRBSR_FSC_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TRBSR_FSC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define TRBMAR_SHARE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TRBMAR_SHARE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define TRBMAR_OUTER_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TRBMAR_OUTER_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define TRBMAR_INNER_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TRBMAR_INNER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TRBTRG_TRG_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TRBTRG_TRG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TRBIDR_FLAG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TRBIDR_PROG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define TRBIDR_ALIGN_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define TRBIDR_ALIGN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SYS_SCXTNUM_EL1 sys_reg(3, 0, 13, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SYS_GMID_EL1 sys_reg(3, 1, 0, 0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Definitions for system register interface to AMU for ARMv8.4 onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Group 0 of activity monitors (architected):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * op0 op1 CRn CRm op2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Counter: 11 011 1101 010:n<3> n<2:0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Type: 11 011 1101 011:n<3> n<2:0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * n: 0-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * Group 1 of activity monitors (auxiliary):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * op0 op1 CRn CRm op2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Counter: 11 011 1101 110:n<3> n<2:0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Type: 11 011 1101 111:n<3> n<2:0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * n: 0-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* AMU v1: Fixed (architecturally defined) activity monitors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define __PMEV_op2(n) ((n) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* VHE encodings for architectural EL0/1 system registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Common SCTLR_ELx flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SCTLR_ELx_DSSBS (BIT(44))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SCTLR_ELx_ATA (BIT(43))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SCTLR_ELx_TCF_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SCTLR_ELx_ENIA_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SCTLR_ELx_ITFSB (BIT(37))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SCTLR_ELx_ENIB (BIT(30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SCTLR_ELx_ENDA (BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define SCTLR_ELx_EE (BIT(25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define SCTLR_ELx_IESB (BIT(21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define SCTLR_ELx_WXN (BIT(19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SCTLR_ELx_ENDB (BIT(13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SCTLR_ELx_I (BIT(12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SCTLR_ELx_SA (BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define SCTLR_ELx_C (BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SCTLR_ELx_A (BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SCTLR_ELx_M (BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* SCTLR_EL2 specific flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (BIT(29)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define ENDIAN_SET_EL2 SCTLR_ELx_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define ENDIAN_SET_EL2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define INIT_SCTLR_EL2_MMU_ON \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define INIT_SCTLR_EL2_MMU_OFF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* SCTLR_EL1 specific flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define SCTLR_EL1_ATA0 (BIT(42))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define SCTLR_EL1_TCF0_SHIFT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define SCTLR_EL1_TCF0_NONE (UL(0x0) << SCTLR_EL1_TCF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define SCTLR_EL1_TCF0_SYNC (UL(0x1) << SCTLR_EL1_TCF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define SCTLR_EL1_TCF0_ASYNC (UL(0x2) << SCTLR_EL1_TCF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define SCTLR_EL1_BT1 (BIT(36))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define SCTLR_EL1_BT0 (BIT(35))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define SCTLR_EL1_UCI (BIT(26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define SCTLR_EL1_E0E (BIT(24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define SCTLR_EL1_SPAN (BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define SCTLR_EL1_NTWE (BIT(18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define SCTLR_EL1_NTWI (BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define SCTLR_EL1_UCT (BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define SCTLR_EL1_DZE (BIT(14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SCTLR_EL1_UMA (BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SCTLR_EL1_SED (BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SCTLR_EL1_ITD (BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SCTLR_EL1_CP15BEN (BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SCTLR_EL1_SA0 (BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) (BIT(29)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #ifdef CONFIG_CPU_BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define ENDIAN_SET_EL1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define INIT_SCTLR_EL1_MMU_OFF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define INIT_SCTLR_EL1_MMU_ON \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* MAIR_ELx memory attributes (used by Linux) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define MAIR_ATTR_DEVICE_GRE UL(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define MAIR_ATTR_NORMAL_NC UL(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define MAIR_ATTR_NORMAL_WT UL(0xbb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define MAIR_ATTR_NORMAL UL(0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define MAIR_ATTR_MASK UL(0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define MAIR_ATTR_NORMAL_iNC_oWB UL(0xf4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Position the attr at the correct index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* id_aa64isar0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define ID_AA64ISAR0_RNDR_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define ID_AA64ISAR0_TLB_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define ID_AA64ISAR0_TS_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define ID_AA64ISAR0_FHM_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define ID_AA64ISAR0_DP_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define ID_AA64ISAR0_SM4_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define ID_AA64ISAR0_SM3_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define ID_AA64ISAR0_SHA3_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define ID_AA64ISAR0_RDM_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define ID_AA64ISAR0_ATOMICS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define ID_AA64ISAR0_CRC32_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define ID_AA64ISAR0_SHA2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define ID_AA64ISAR0_SHA1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define ID_AA64ISAR0_AES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define ID_AA64ISAR0_TLB_RANGE_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define ID_AA64ISAR0_TLB_RANGE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* id_aa64isar1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define ID_AA64ISAR1_I8MM_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define ID_AA64ISAR1_DGH_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define ID_AA64ISAR1_BF16_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define ID_AA64ISAR1_SPECRES_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define ID_AA64ISAR1_SB_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ID_AA64ISAR1_FRINTTS_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define ID_AA64ISAR1_GPI_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define ID_AA64ISAR1_GPA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define ID_AA64ISAR1_LRCPC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define ID_AA64ISAR1_FCMA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define ID_AA64ISAR1_JSCVT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define ID_AA64ISAR1_API_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define ID_AA64ISAR1_APA_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define ID_AA64ISAR1_DPB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define ID_AA64ISAR1_APA_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define ID_AA64ISAR1_APA_ARCHITECTED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define ID_AA64ISAR1_APA_ARCH_EPAC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define ID_AA64ISAR1_APA_ARCH_EPAC2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define ID_AA64ISAR1_API_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define ID_AA64ISAR1_API_IMP_DEF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define ID_AA64ISAR1_API_IMP_DEF_EPAC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define ID_AA64ISAR1_GPA_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define ID_AA64ISAR1_GPI_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define ID_AA64ISAR1_GPI_IMP_DEF 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* id_aa64isar2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define ID_AA64ISAR2_CLEARBHB_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define ID_AA64ISAR2_RPRES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define ID_AA64ISAR2_WFXT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define ID_AA64ISAR2_RPRES_8BIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define ID_AA64ISAR2_RPRES_12BIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * Value 0x1 has been removed from the architecture, and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * reserved, but has not yet been removed from the ARM ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * as of ARM DDI 0487G.b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define ID_AA64ISAR2_WFXT_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* id_aa64pfr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define ID_AA64PFR0_CSV3_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define ID_AA64PFR0_CSV2_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define ID_AA64PFR0_DIT_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define ID_AA64PFR0_AMU_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define ID_AA64PFR0_MPAM_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define ID_AA64PFR0_SEL2_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define ID_AA64PFR0_SVE_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define ID_AA64PFR0_RAS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define ID_AA64PFR0_GIC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define ID_AA64PFR0_ASIMD_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define ID_AA64PFR0_FP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define ID_AA64PFR0_EL3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define ID_AA64PFR0_EL2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define ID_AA64PFR0_EL1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define ID_AA64PFR0_EL0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define ID_AA64PFR0_AMU 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define ID_AA64PFR0_SVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define ID_AA64PFR0_RAS_V1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define ID_AA64PFR0_FP_NI 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define ID_AA64PFR0_FP_SUPPORTED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define ID_AA64PFR0_ASIMD_NI 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define ID_AA64PFR0_EL1_32BIT_64BIT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* id_aa64pfr1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define ID_AA64PFR1_MPAMFRAC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define ID_AA64PFR1_RASFRAC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define ID_AA64PFR1_MTE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define ID_AA64PFR1_SSBS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define ID_AA64PFR1_BT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define ID_AA64PFR1_SSBS_PSTATE_NI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define ID_AA64PFR1_BT_BTI 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define ID_AA64PFR1_MTE_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define ID_AA64PFR1_MTE_EL0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define ID_AA64PFR1_MTE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* id_aa64zfr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define ID_AA64ZFR0_F64MM_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define ID_AA64ZFR0_F32MM_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define ID_AA64ZFR0_I8MM_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define ID_AA64ZFR0_SM4_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define ID_AA64ZFR0_SHA3_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define ID_AA64ZFR0_BF16_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define ID_AA64ZFR0_BITPERM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define ID_AA64ZFR0_AES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define ID_AA64ZFR0_SVEVER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define ID_AA64ZFR0_F64MM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define ID_AA64ZFR0_F32MM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define ID_AA64ZFR0_I8MM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define ID_AA64ZFR0_BF16 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define ID_AA64ZFR0_SM4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define ID_AA64ZFR0_SHA3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define ID_AA64ZFR0_BITPERM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define ID_AA64ZFR0_AES 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define ID_AA64ZFR0_AES_PMULL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define ID_AA64ZFR0_SVEVER_SVE2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* id_aa64mmfr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define ID_AA64MMFR0_ECV_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define ID_AA64MMFR0_FGT_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define ID_AA64MMFR0_EXS_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define ID_AA64MMFR0_TGRAN4_2_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define ID_AA64MMFR0_TGRAN64_2_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define ID_AA64MMFR0_TGRAN16_2_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define ID_AA64MMFR0_TGRAN4_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define ID_AA64MMFR0_TGRAN64_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define ID_AA64MMFR0_TGRAN16_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define ID_AA64MMFR0_SNSMEM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define ID_AA64MMFR0_ASID_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define ID_AA64MMFR0_PARANGE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define ID_AA64MMFR0_TGRAN4_NI 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define ID_AA64MMFR0_TGRAN64_NI 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define ID_AA64MMFR0_TGRAN16_NI 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define ID_AA64MMFR0_PARANGE_48 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define ID_AA64MMFR0_PARANGE_52 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #ifdef CONFIG_ARM64_PA_BITS_52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* id_aa64mmfr1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define ID_AA64MMFR1_ECBHB_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define ID_AA64MMFR1_AFP_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define ID_AA64MMFR1_ETS_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define ID_AA64MMFR1_TWED_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define ID_AA64MMFR1_XNX_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define ID_AA64MMFR1_SPECSEI_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define ID_AA64MMFR1_PAN_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define ID_AA64MMFR1_LOR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define ID_AA64MMFR1_HPD_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define ID_AA64MMFR1_VHE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define ID_AA64MMFR1_HADBS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define ID_AA64MMFR1_VMIDBITS_8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define ID_AA64MMFR1_VMIDBITS_16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* id_aa64mmfr2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define ID_AA64MMFR2_E0PD_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define ID_AA64MMFR2_EVT_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define ID_AA64MMFR2_BBM_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define ID_AA64MMFR2_TTL_SHIFT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define ID_AA64MMFR2_FWB_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define ID_AA64MMFR2_IDS_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define ID_AA64MMFR2_AT_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define ID_AA64MMFR2_ST_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define ID_AA64MMFR2_NV_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define ID_AA64MMFR2_CCIDX_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define ID_AA64MMFR2_LVA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define ID_AA64MMFR2_IESB_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define ID_AA64MMFR2_LSM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define ID_AA64MMFR2_UAO_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define ID_AA64MMFR2_CNP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* id_aa64dfr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define ID_AA64DFR0_TRBE_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define ID_AA64DFR0_TRACE_FILT_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define ID_AA64DFR0_PMSVER_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define ID_AA64DFR0_WRPS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define ID_AA64DFR0_BRPS_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define ID_AA64DFR0_PMUVER_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define ID_AA64DFR0_TRACEVER_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define ID_AA64DFR0_DEBUGVER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define ID_AA64DFR0_PMUVER_8_0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define ID_AA64DFR0_PMUVER_8_1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define ID_AA64DFR0_PMUVER_8_4 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define ID_AA64DFR0_PMUVER_8_5 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define ID_DFR0_PERFMON_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define ID_DFR0_PERFMON_8_0 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define ID_DFR0_PERFMON_8_1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define ID_DFR0_PERFMON_8_4 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define ID_DFR0_PERFMON_8_5 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define ID_ISAR4_SWP_FRAC_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define ID_ISAR4_PSR_M_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define ID_ISAR4_BARRIER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define ID_ISAR4_SMC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define ID_ISAR4_WRITEBACK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define ID_ISAR4_WITHSHIFTS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define ID_ISAR4_UNPRIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define ID_DFR1_MTPMU_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define ID_ISAR0_DIVIDE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define ID_ISAR0_DEBUG_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define ID_ISAR0_COPROC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define ID_ISAR0_CMPBRANCH_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define ID_ISAR0_BITFIELD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define ID_ISAR0_BITCOUNT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define ID_ISAR0_SWAP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define ID_ISAR5_RDM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define ID_ISAR5_CRC32_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define ID_ISAR5_SHA2_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define ID_ISAR5_SHA1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define ID_ISAR5_AES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define ID_ISAR5_SEVL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define ID_ISAR6_I8MM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define ID_ISAR6_BF16_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define ID_ISAR6_SPECRES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define ID_ISAR6_SB_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define ID_ISAR6_FHM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define ID_ISAR6_DP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define ID_ISAR6_JSCVT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define ID_MMFR0_INNERSHR_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define ID_MMFR0_FCSE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define ID_MMFR0_AUXREG_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define ID_MMFR0_TCM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define ID_MMFR0_SHARELVL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define ID_MMFR0_OUTERSHR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define ID_MMFR0_PMSA_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define ID_MMFR0_VMSA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define ID_MMFR4_EVT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define ID_MMFR4_CCIDX_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define ID_MMFR4_LSM_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define ID_MMFR4_HPDS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define ID_MMFR4_CNP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define ID_MMFR4_XNX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define ID_MMFR4_AC2_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define ID_MMFR4_SPECSEI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define ID_MMFR5_ETS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define ID_PFR0_DIT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define ID_PFR0_CSV2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define ID_PFR0_STATE3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define ID_PFR0_STATE2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define ID_PFR0_STATE1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define ID_PFR0_STATE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define ID_DFR0_PERFMON_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define ID_DFR0_MPROFDBG_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define ID_DFR0_MMAPTRC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define ID_DFR0_COPTRC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define ID_DFR0_MMAPDBG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define ID_DFR0_COPSDBG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define ID_DFR0_COPDBG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define ID_PFR2_SSBS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define ID_PFR2_CSV3_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define MVFR0_FPROUND_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define MVFR0_FPSHVEC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define MVFR0_FPSQRT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define MVFR0_FPDIVIDE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define MVFR0_FPTRAP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define MVFR0_FPDP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define MVFR0_FPSP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define MVFR0_SIMD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define MVFR1_SIMDFMAC_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define MVFR1_FPHP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define MVFR1_SIMDHP_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define MVFR1_SIMDSP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define MVFR1_SIMDINT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define MVFR1_SIMDLS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define MVFR1_FPDNAN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define MVFR1_FPFTZ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define ID_PFR1_GIC_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define ID_PFR1_VIRT_FRAC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define ID_PFR1_SEC_FRAC_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define ID_PFR1_GENTIMER_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define ID_PFR1_VIRTUALIZATION_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define ID_PFR1_MPROGMOD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define ID_PFR1_SECURITY_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define ID_PFR1_PROGMOD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #if defined(CONFIG_ARM64_4K_PAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #elif defined(CONFIG_ARM64_16K_PAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #elif defined(CONFIG_ARM64_64K_PAGES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define MVFR2_FPMISC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define MVFR2_SIMDMISC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define DCZID_DZP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define DCZID_BS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * are reserved by the SVE architecture for future expansion of the LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * field, with compatible semantics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define ZCR_ELx_LEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define ZCR_ELx_LEN_SIZE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define ZCR_ELx_LEN_MASK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* TCR EL1 Bit Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define SYS_TCR_EL1_TCMA1 (BIT(58))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define SYS_TCR_EL1_TCMA0 (BIT(57))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* GCR_EL1 Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define SYS_GCR_EL1_RRND (BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define SYS_GCR_EL1_EXCL_MASK 0xffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #ifdef CONFIG_KASAN_HW_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* RGSR_EL1 Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define SYS_RGSR_EL1_TAG_MASK 0xfUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define SYS_RGSR_EL1_SEED_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* GMID_EL1 field definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define SYS_GMID_EL1_BS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define SYS_GMID_EL1_BS_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* TFSR{,E0}_EL1 bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define SYS_TFSR_EL1_TF0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define SYS_TFSR_EL1_TF1_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define SYS_MPIDR_SAFE_VAL (BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define TRFCR_ELx_TS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define TRFCR_EL2_CX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define TRFCR_ELx_ExTRE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define TRFCR_ELx_E0TRE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .equ .L__reg_num_x\num, \num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .equ .L__reg_num_xzr, 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .macro mrs_s, rt, sreg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .macro msr_s, sreg, rt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #include <linux/build_bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #include <asm/alternative.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define __DEFINE_MRS_MSR_S_REGNUM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) " .equ .L__reg_num_x\\num, \\num\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) " .endr\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) " .equ .L__reg_num_xzr, 31\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define DEFINE_MRS_S \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) __DEFINE_MRS_MSR_S_REGNUM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) " .macro mrs_s, rt, sreg\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) " .endm\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define DEFINE_MSR_S \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) __DEFINE_MRS_MSR_S_REGNUM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) " .macro msr_s, sreg, rt\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) " .endm\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define UNDEFINE_MRS_S \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) " .purgem mrs_s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define UNDEFINE_MSR_S \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) " .purgem msr_s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define __mrs_s(v, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) DEFINE_MRS_S \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) " mrs_s " v ", " __stringify(r) "\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) UNDEFINE_MRS_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define __msr_s(r, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) DEFINE_MSR_S \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) " msr_s " __stringify(r) ", " v "\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) UNDEFINE_MSR_S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * Unlike read_cpuid, calls to read_sysreg are never expected to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * optimized away or replaced with synthetic values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define read_sysreg(r) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u64 __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * The "Z" constraint normally means a zero immediate, but when combined with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * the "%x0" template means XZR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define write_sysreg(v, r) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u64 __val = (u64)(v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) asm volatile("msr " __stringify(r) ", %x0" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) : : "rZ" (__val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * For registers without architectural names, or simply unsupported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * GAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define read_sysreg_s(r) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u64 __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define write_sysreg_s(v, r) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u64 __val = (u64)(v); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * set mask are set. Other bits are left as-is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define sysreg_clear_set(sysreg, clear, set) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u64 __scs_val = read_sysreg(sysreg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (__scs_new != __scs_val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) write_sysreg(__scs_new, sysreg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define sysreg_clear_set_s(sysreg, clear, set) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) u64 __scs_val = read_sysreg_s(sysreg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (__scs_new != __scs_val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) write_sysreg_s(__scs_new, sysreg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define read_sysreg_par() ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u64 par; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) par = read_sysreg(par_el1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) par; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #endif /* __ASM_SYSREG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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