Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2020 Google LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef __ASM_RWONCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define __ASM_RWONCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #if defined(CONFIG_LTO) && !defined(__ASSEMBLY__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/compiler_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/alternative-macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef BUILD_VDSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_AS_HAS_LDAPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __LOAD_RCPC(sfx, regs...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	ALTERNATIVE(							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		"ldar"	#sfx "\t" #regs,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		".arch_extension rcpc\n"				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		"ldapr"	#sfx "\t" #regs,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	ARM64_HAS_LDAPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __LOAD_RCPC(sfx, regs...)	"ldar" #sfx "\t" #regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif /* CONFIG_AS_HAS_LDAPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * When building with LTO, there is an increased risk of the compiler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * converting an address dependency headed by a READ_ONCE() invocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * into a control dependency and consequently allowing for harmful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * reordering by the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * Ensure that such transformations are harmless by overriding the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * READ_ONCE() definition with one that provides RCpc acquire semantics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * when building with LTO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define __READ_ONCE(x)							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ({									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	typeof(&(x)) __x = &(x);					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	int atomic = 1;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	union { __unqual_scalar_typeof(*__x) __val; char __c[1]; } __u;	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	switch (sizeof(x)) {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	case 1:								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		asm volatile(__LOAD_RCPC(b, %w0, %1)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			: "=r" (*(__u8 *)__u.__c)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			: "Q" (*__x) : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		break;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	case 2:								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		asm volatile(__LOAD_RCPC(h, %w0, %1)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			: "=r" (*(__u16 *)__u.__c)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			: "Q" (*__x) : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		break;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	case 4:								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		asm volatile(__LOAD_RCPC(, %w0, %1)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			: "=r" (*(__u32 *)__u.__c)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			: "Q" (*__x) : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		break;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	case 8:								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		asm volatile(__LOAD_RCPC(, %0, %1)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			: "=r" (*(__u64 *)__u.__c)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			: "Q" (*__x) : "memory");			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		break;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	default:							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		atomic = 0;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	}								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	atomic ? (typeof(*__x))__u.__val : (*(volatile typeof(__x))__x);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif	/* !BUILD_VDSO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif	/* CONFIG_LTO && !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm-generic/rwonce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif	/* __ASM_RWONCE_H */