Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __ASM_PGTABLE_HWDEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __ASM_PGTABLE_HWDEF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Number of page-table levels required to address 'va_bits' wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * due to build issues. So we open code DIV_ROUND_UP here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * which gets simplified as :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Size mapped by an entry at level n ( 0 <= n <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * in the final page. The maximum number of translation levels supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * the architecture is 4. Hence, starting at level n, we have further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * ((4 - n) - 1) levels of translation excluding the offset within the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * So, the total number of bits mapped by an entry at level n is :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * Rearranging it a bit we get :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *   (4 - n) * (PAGE_SHIFT - 3) + 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * PMD_SHIFT determines the size a level 2 page table entry can map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #if CONFIG_PGTABLE_LEVELS > 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PMD_MASK		(~(PMD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PTRS_PER_PMD		PTRS_PER_PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * PUD_SHIFT determines the size a level 1 page table entry can map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #if CONFIG_PGTABLE_LEVELS > 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PUD_MASK		(~(PUD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PTRS_PER_PUD		PTRS_PER_PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * PGDIR_SHIFT determines the size a top-level page table entry can map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * (depending on the configuration, this level can be 0, 1 or 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PGDIR_MASK		(~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * Section address mask and size definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SECTION_SHIFT		PMD_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SECTION_MASK		(~(SECTION_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * Contiguous page definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CONT_PTE_SHIFT		(CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CONT_PTES		(1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CONT_PMD_SHIFT		(CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CONT_PMDS		(1 << (CONT_PMD_SHIFT - PMD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * Hardware page table definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * Level 1 descriptor (PUD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PUD_TYPE_MASK		(_AT(pudval_t, 3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PUD_SECT_RDONLY		(_AT(pudval_t, 1) << 7)		/* AP[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * Level 2 descriptor (PMD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * Section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * Level 3 descriptor (PTE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PTE_VALID		(_AT(pteval_t, 1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PTE_GP			(_AT(pteval_t, 1) << 50)	/* BTI guarded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_ARM64_PA_BITS_52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PTE_ADDR_HIGH		(_AT(pteval_t, 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PTE_ADDR_MASK		(PTE_ADDR_LOW | PTE_ADDR_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PTE_ADDR_MASK		PTE_ADDR_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * Memory Attribute override for Stage-2 (MemAttr[3:0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * Highest possible physical address supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TTBR_CNP_BIT		(UL(1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * TCR flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TCR_T0SZ_OFFSET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TCR_T1SZ_OFFSET		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TCR_TxSZ_WIDTH		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TCR_EPD0_SHIFT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TCR_IRGN0_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TCR_EPD1_SHIFT		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TCR_IRGN1_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TCR_ORGN0_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TCR_ORGN1_SHIFT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TCR_SH0_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TCR_SH1_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TCR_TG0_SHIFT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TCR_TG1_SHIFT		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TCR_IPS_SHIFT		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TCR_A1			(UL(1) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TCR_ASID16		(UL(1) << 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TCR_TBI0		(UL(1) << 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TCR_TBI1		(UL(1) << 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TCR_HA			(UL(1) << 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TCR_HD			(UL(1) << 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TCR_TBID1		(UL(1) << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TCR_NFD0		(UL(1) << 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TCR_NFD1		(UL(1) << 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TCR_E0PD0		(UL(1) << 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TCR_E0PD1		(UL(1) << 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * TTBR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #ifdef CONFIG_ARM64_PA_BITS_52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * This should be GENMASK_ULL(47, 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * TTBR_ELx[1] is RES0 in this configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TTBR_BADDR_MASK_52	(((UL(1) << 46) - 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #ifdef CONFIG_ARM64_VA_BITS_52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif