Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2013 - ARM Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Marc Zyngier <marc.zyngier@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef __ASM_ESR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define __ASM_ESR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/sysreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define ESR_ELx_EC_UNKNOWN	(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define ESR_ELx_EC_WFx		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* Unallocated EC: 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ESR_ELx_EC_CP15_32	(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ESR_ELx_EC_CP15_64	(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ESR_ELx_EC_CP14_MR	(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define ESR_ELx_EC_CP14_LS	(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define ESR_ELx_EC_FP_ASIMD	(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* Unallocated EC: 0x0A - 0x0B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ESR_ELx_EC_CP14_64	(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ESR_ELx_EC_BTI		(0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ESR_ELx_EC_ILL		(0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Unallocated EC: 0x0F - 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ESR_ELx_EC_SVC32	(0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Unallocated EC: 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ESR_ELx_EC_SVC64	(0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ESR_ELx_EC_SYS64	(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ESR_ELx_EC_SVE		(0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Unallocated EC: 0x1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Unallocated EC: 0x1D - 0x1E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ESR_ELx_EC_IABT_LOW	(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ESR_ELx_EC_IABT_CUR	(0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ESR_ELx_EC_PC_ALIGN	(0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Unallocated EC: 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define ESR_ELx_EC_DABT_LOW	(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ESR_ELx_EC_DABT_CUR	(0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ESR_ELx_EC_SP_ALIGN	(0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Unallocated EC: 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ESR_ELx_EC_FP_EXC32	(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* Unallocated EC: 0x29 - 0x2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ESR_ELx_EC_FP_EXC64	(0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Unallocated EC: 0x2D - 0x2E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ESR_ELx_EC_SERROR	(0x2F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ESR_ELx_EC_BREAKPT_LOW	(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ESR_ELx_EC_BREAKPT_CUR	(0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ESR_ELx_EC_SOFTSTP_LOW	(0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define ESR_ELx_EC_SOFTSTP_CUR	(0x33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ESR_ELx_EC_WATCHPT_LOW	(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define ESR_ELx_EC_WATCHPT_CUR	(0x35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Unallocated EC: 0x36 - 0x37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ESR_ELx_EC_BKPT32	(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Unallocated EC: 0x39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Unallocated EC: 0x3B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define ESR_ELx_EC_BRK64	(0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Unallocated EC: 0x3D - 0x3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define ESR_ELx_EC_MAX		(0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define ESR_ELx_EC_SHIFT	(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define ESR_ELx_EC_WIDTH	(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define ESR_ELx_IL_SHIFT	(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ESR_ELx_IL		(UL(1) << ESR_ELx_IL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* ISS field definitions shared by different classes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define ESR_ELx_WNR_SHIFT	(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ESR_ELx_WNR		(UL(1) << ESR_ELx_WNR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* Asynchronous Error Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ESR_ELx_IDS_SHIFT	(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ESR_ELx_IDS		(UL(1) << ESR_ELx_IDS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ESR_ELx_AET_SHIFT	(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ESR_ELx_AET		(UL(0x7) << ESR_ELx_AET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ESR_ELx_AET_UC		(UL(0) << ESR_ELx_AET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ESR_ELx_AET_UEU		(UL(1) << ESR_ELx_AET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ESR_ELx_AET_UEO		(UL(2) << ESR_ELx_AET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ESR_ELx_AET_UER		(UL(3) << ESR_ELx_AET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ESR_ELx_AET_CE		(UL(6) << ESR_ELx_AET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* Shared ISS field definitions for Data/Instruction aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ESR_ELx_SET_SHIFT	(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ESR_ELx_SET_MASK	(UL(3) << ESR_ELx_SET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ESR_ELx_FnV_SHIFT	(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ESR_ELx_FnV		(UL(1) << ESR_ELx_FnV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ESR_ELx_EA_SHIFT	(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ESR_ELx_EA		(UL(1) << ESR_ELx_EA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ESR_ELx_S1PTW_SHIFT	(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ESR_ELx_S1PTW		(UL(1) << ESR_ELx_S1PTW_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ESR_ELx_FSC		(0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ESR_ELx_FSC_TYPE	(0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ESR_ELx_FSC_LEVEL	(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ESR_ELx_FSC_EXTABT	(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ESR_ELx_FSC_MTE		(0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ESR_ELx_FSC_SERROR	(0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ESR_ELx_FSC_ACCESS	(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ESR_ELx_FSC_FAULT	(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ESR_ELx_FSC_PERM	(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ESR_ELx_FSC_TLBCONF	(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* ISS field definitions for Data Aborts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ESR_ELx_ISV_SHIFT	(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ESR_ELx_ISV		(UL(1) << ESR_ELx_ISV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ESR_ELx_SAS_SHIFT	(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ESR_ELx_SSE_SHIFT	(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ESR_ELx_SSE		(UL(1) << ESR_ELx_SSE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ESR_ELx_SRT_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ESR_ELx_SF_SHIFT	(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ESR_ELx_SF 		(UL(1) << ESR_ELx_SF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ESR_ELx_AR_SHIFT	(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ESR_ELx_AR 		(UL(1) << ESR_ELx_AR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ESR_ELx_CM_SHIFT	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* ISS field definitions for exceptions taken in to Hyp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ESR_ELx_CV		(UL(1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ESR_ELx_COND_SHIFT	(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DISR_EL1_IDS		(UL(1) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * different things in the future...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* ESR value templates for specific events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				 ESR_ELx_WFx_ISS_WFI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* BRK instruction trap from AArch64 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* ISS field definitions for System instruction traps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ESR_ELx_SYS64_ISS_DIR_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ESR_ELx_SYS64_ISS_DIR_READ	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ESR_ELx_SYS64_ISS_RT_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ESR_ELx_SYS64_ISS_CRM_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ESR_ELx_SYS64_ISS_CRN_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ESR_ELx_SYS64_ISS_OP1_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ESR_ELx_SYS64_ISS_OP2_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ESR_ELx_SYS64_ISS_OP0_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					 ESR_ELx_SYS64_ISS_OP1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 					 ESR_ELx_SYS64_ISS_OP2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					 ESR_ELx_SYS64_ISS_CRN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					 ESR_ELx_SYS64_ISS_CRM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 					 ESR_ELx_SYS64_ISS_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ESR_ELx_SYS64_ISS_RT(esr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * User space cache operations have the following sysreg encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * in System instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 						 ESR_ELx_SYS64_ISS_OP1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 						 ESR_ELx_SYS64_ISS_OP2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 						 ESR_ELx_SYS64_ISS_CRN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 						 ESR_ELx_SYS64_ISS_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				 ESR_ELx_SYS64_ISS_DIR_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  * User space MRS operations which are supported for emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * have the following sysreg encoding in System instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 						 ESR_ELx_SYS64_ISS_OP1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 						 ESR_ELx_SYS64_ISS_CRN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 						 ESR_ELx_SYS64_ISS_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				 ESR_ELx_SYS64_ISS_DIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					 ESR_ELx_SYS64_ISS_DIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 					 ESR_ELx_SYS64_ISS_DIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 					 ESR_ELx_SYS64_ISS_DIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define esr_sys64_to_sysreg(e)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		 ESR_ELx_SYS64_ISS_OP0_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define esr_cp15_to_sysreg(e)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	sys_reg(3,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		 ESR_ELx_SYS64_ISS_OP1_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		 ESR_ELx_SYS64_ISS_CRN_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 ESR_ELx_SYS64_ISS_CRM_SHIFT),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >>		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		 ESR_ELx_SYS64_ISS_OP2_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * ISS field definitions for floating-point exception traps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * (FP_EXC_32/FP_EXC_64).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * (The FPEXC_* constants are used instead for common bits.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * ISS field definitions for CP15 accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 					 ESR_ELx_CP15_32_ISS_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 					 ESR_ELx_CP15_64_ISS_DIR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					 ESR_ELx_CP15_64_ISS_DIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 					 ESR_ELx_CP15_32_ISS_DIR_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline bool esr_is_data_abort(u32 esr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	const u32 ec = ESR_ELx_EC(esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) const char *esr_get_class_string(u32 esr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif /* __ASSEMBLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif /* __ASM_ESR_H */