^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm64/include/asm/cpucaps.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __ASM_CPUCAPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __ASM_CPUCAPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ARM64_WORKAROUND_CLEAN_CACHE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ARM64_WORKAROUND_845719 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ARM64_HAS_SYSREG_GIC_CPUIF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ARM64_HAS_PAN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARM64_HAS_LSE_ATOMICS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARM64_WORKAROUND_CAVIUM_23154 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARM64_WORKAROUND_834220 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ARM64_HAS_NO_HW_PREFETCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ARM64_HAS_UAO 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ARM64_ALT_PAN_NOT_UAO 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ARM64_HAS_VIRT_HOST_EXTN 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARM64_WORKAROUND_CAVIUM_27456 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Unreliable: use system_supports_32bit_el0() instead. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ARM64_HAS_32BIT_EL0_DO_NOT_USE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ARM64_SPECTRE_V3A 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ARM64_HAS_CNP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ARM64_HAS_NO_FPSIMD 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ARM64_WORKAROUND_REPEAT_TLBI 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARM64_WORKAROUND_858921 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ARM64_WORKAROUND_CAVIUM_30115 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ARM64_HAS_DCPOP 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ARM64_SVE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ARM64_UNMAP_KERNEL_AT_EL0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ARM64_SPECTRE_V2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ARM64_HAS_RAS_EXTN 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ARM64_WORKAROUND_843419 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ARM64_HAS_CACHE_IDC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ARM64_HAS_CACHE_DIC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ARM64_HW_DBM 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ARM64_SPECTRE_V4 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ARM64_MISMATCHED_CACHE_TYPE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ARM64_HAS_STAGE2_FWB 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ARM64_HAS_CRC32 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ARM64_SSBS 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ARM64_WORKAROUND_1418040 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ARM64_HAS_SB 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ARM64_WORKAROUND_SPECULATIVE_AT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ARM64_HAS_ADDRESS_AUTH_ARCH 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ARM64_HAS_GENERIC_AUTH_ARCH 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARM64_HAS_IRQ_PRIO_MASKING 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ARM64_HAS_DCPODP 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ARM64_WORKAROUND_1463225 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ARM64_WORKAROUND_1542419 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ARM64_HAS_E0PD 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ARM64_HAS_RNG 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ARM64_HAS_AMU_EXTN 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ARM64_HAS_ADDRESS_AUTH 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ARM64_HAS_GENERIC_AUTH 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ARM64_HAS_32BIT_EL1 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ARM64_BTI 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ARM64_HAS_ARMv8_4_TTL 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ARM64_HAS_TLB_RANGE 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ARM64_MTE 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ARM64_WORKAROUND_1508412 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ARM64_HAS_LDAPR 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ARM64_KVM_PROTECTED_MODE 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ARM64_WORKAROUND_TSB_FLUSH_FAILURE 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ARM64_SPECTRE_BHB 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* kabi: reserve 63 - 76 for future cpu capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ARM64_NCAPS 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif /* __ASM_CPUCAPS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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