^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __ASM_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __ASM_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CTR_L1IP_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CTR_L1IP_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CTR_DMINLINE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CTR_IMINLINE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CTR_IMINLINE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CTR_ERG_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CTR_CWG_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CTR_CWG_MASK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CTR_IDC_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CTR_DIC_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CTR_CACHE_MINLINE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ICACHE_POLICY_VPIPT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ICACHE_POLICY_RESERVED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ICACHE_POLICY_VIPT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ICACHE_POLICY_PIPT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define L1_CACHE_SHIFT (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLIDR_LOUU_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLIDR_LOC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLIDR_LOUIS_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Memory returned by kmalloc() may be used for DMA, so we must make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * sure that all such allocations are cache aligned. Otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * unrelated code may cause parts of the buffer to be read into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * cache before the transfer is done, causing old data to be seen by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ARCH_DMA_MINALIGN (128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_KASAN_SW_TAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #elif defined(CONFIG_KASAN_HW_TAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ARCH_SLAB_MINALIGN MTE_GRANULE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ICACHEF_ALIASING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ICACHEF_VPIPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern unsigned long __icache_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * permitted in the I-cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline int icache_is_aliasing(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return test_bit(ICACHEF_ALIASING, &__icache_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static __always_inline int icache_is_vpipt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return test_bit(ICACHEF_VPIPT, &__icache_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline u32 cache_type_cwg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define __read_mostly __section(".data..read_mostly")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline int cache_line_size_of_cpu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 cwg = cache_type_cwg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int cache_line_size(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Read the effective value of CTR_EL0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * section D10.2.33 "CTR_EL0, Cache Type Register" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * CTR_EL0.IDC reports the data cache clean requirements for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * instruction to data coherence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 0 - dcache clean to PoU is required unless :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 1 - dcache clean to PoU is not required for i-to-d coherence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * This routine provides the CTR_EL0 with the IDC field updated to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * effective state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 ctr = read_cpuid_cachetype();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!(ctr & BIT(CTR_IDC_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u64 clidr = read_sysreg(clidr_el1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (CLIDR_LOC(clidr) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ctr |= BIT(CTR_IDC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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