^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_ASM_UACCESS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_ASM_UACCESS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/alternative-macros.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/kernel-pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <asm/sysreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * User access enabling/disabling macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef CONFIG_ARM64_SW_TTBR0_PAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .macro __uaccess_ttbr0_disable, tmp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) mrs \tmp1, ttbr1_el1 // swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) bic \tmp1, \tmp1, #TTBR_ASID_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) sub \tmp1, \tmp1, #PAGE_SIZE // reserved_pg_dir just before swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) add \tmp1, \tmp1, #PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) msr ttbr1_el1, \tmp1 // set reserved ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .macro __uaccess_ttbr0_enable, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) get_current_task \tmp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) mrs \tmp2, ttbr1_el1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extr \tmp2, \tmp2, \tmp1, #48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ror \tmp2, \tmp2, #16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) msr ttbr1_el1, \tmp2 // set the active ASID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) isb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .macro uaccess_ttbr0_disable, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) alternative_if_not ARM64_HAS_PAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) save_and_disable_irq \tmp2 // avoid preemption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __uaccess_ttbr0_disable \tmp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) restore_irq \tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) alternative_if_not ARM64_HAS_PAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) save_and_disable_irq \tmp3 // avoid preemption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __uaccess_ttbr0_enable \tmp1, \tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) restore_irq \tmp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) alternative_else_nop_endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .macro uaccess_ttbr0_disable, tmp1, tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Generate the assembly for LDTR/STTR with exception table entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * This is complicated as there is no post-increment or pair versions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * unprivileged instructions, and USER() only works for single instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .macro uao_ldp l, reg1, reg2, addr, post_inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 8888: ldtr \reg1, [\addr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 8889: ldtr \reg2, [\addr, #8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) add \addr, \addr, \post_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) _asm_extable 8888b,\l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) _asm_extable 8889b,\l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .macro uao_stp l, reg1, reg2, addr, post_inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 8888: sttr \reg1, [\addr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 8889: sttr \reg2, [\addr, #8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) add \addr, \addr, \post_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) _asm_extable 8888b,\l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) _asm_extable 8889b,\l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 8888: \alt_inst \reg, [\addr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) add \addr, \addr, \post_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) _asm_extable 8888b,\l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif