Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_ARCHRANDOM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_ARCHRANDOM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifdef CONFIG_ARCH_RANDOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static inline bool __arm64_rndr(unsigned long *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	bool ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 * Reads of RNDR set PSTATE.NZCV to 0b0000 on success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 * and set PSTATE.NZCV to 0b0100 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		__mrs_s("%0", SYS_RNDR_EL0) "\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	"	cset %w1, ne\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	: "=r" (*v), "=r" (ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	: "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	return ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static inline bool __must_check arch_get_random_long(unsigned long *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline bool __must_check arch_get_random_int(unsigned int *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	 * Only support the generic interface after we have detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	 * the system wide capability, avoiding complexity with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	 * cpufeature code and with potential scheduling between CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	 * with and without the feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	if (!cpus_have_const_cap(ARM64_HAS_RNG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return __arm64_rndr(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	bool ok = arch_get_random_seed_long(&val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	*v = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	return ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline bool __init __early_cpu_has_rndr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	/* Open code as we run prior to the first call to cpufeature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	unsigned long ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	return (ftr >> ID_AA64ISAR0_RNDR_SHIFT) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline bool __init __must_check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) arch_get_random_seed_long_early(unsigned long *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	WARN_ON(system_state != SYSTEM_BOOTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	if (!__early_cpu_has_rndr())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	return __arm64_rndr(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define arch_get_random_seed_long_early arch_get_random_seed_long_early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* CONFIG_ARCH_RANDOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif /* _ASM_ARCHRANDOM_H */