// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/memory/rk3368-dram.h>
#include <dt-bindings/clock/rockchip-ddr.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
dram_spd_bin = <DDR3_DEFAULT>;
sr_idle = <1>;
pd_idle = <0x20>;
dram_dll_disb_freq = <300>;
phy_dll_disb_freq = <400>;
dram_odt_disb_freq = <333>;
phy_odt_disb_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
lpddr2_drv = <LP2_DS_34ohm>; /* lpddr2 not supported odt */
phy_clk_drv = <PHY_RON_45ohm>;
phy_cmd_drv = <PHY_RON_34ohm>;
phy_dqs_drv = <PHY_RON_34ohm>;
phy_odt = <PHY_RTT_279ohm>;
ddr_2t = <ENABLE_DDR_2T>;
};
};